path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.233090                       # Number of seconds simulated
sim_ticks                                233090215000                       # Number of ticks simulated
final_tick                               233090215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  75004                       # Simulator instruction rate (inst/s)
host_op_rate                                    84493                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               34350324                       # Simulator tick rate (ticks/s)
host_mem_usage                                 237136                       # Number of bytes of host memory used
host_seconds                                  6785.68                       # Real time elapsed on the host
sim_insts                                   508954971                       # Number of instructions simulated
sim_ops                                     573341532                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read                    15203328                       # Number of bytes read from this memory
system.physmem.bytes_inst_read                 248448                       # Number of instructions bytes read from this memory
system.physmem.bytes_written                 10942400                       # Number of bytes written to this memory
system.physmem.num_reads                       237552                       # Number of read requests responded to by this memory
system.physmem.num_writes                      170975                       # Number of write requests responded to by this memory
system.physmem.num_other                            0                       # Number of other requests responded to by this memory
system.physmem.bw_read                       65225080                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read                   1065888                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write                      46944914                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total                     112169994                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        466180431                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                200556895                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          157701783                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect           13206687                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups             107805920                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 98841530                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                 10112840                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect             2450569                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          137282908                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      897241370                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   200556895                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          108954370                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     197651477                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                54011479                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               89011796                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  101                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1558                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                 126941311                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               3919273                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          462356637                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.264737                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.102062                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                264718484     57.25%     57.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 16102215      3.48%     60.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 21528039      4.66%     65.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 22972257      4.97%     70.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 24519479      5.30%     75.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 13176471      2.85%     78.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 13363017      2.89%     81.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 12910820      2.79%     84.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 73065855     15.80%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            462356637                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.430213                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.924665                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                152349400                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              84610781                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 182515551                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               4600527                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               38280378                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             32264539                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                131208                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              977458438                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                310007                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               38280378                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                165802120                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 6702227                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       64599197                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 173513863                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13458852                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              899149269                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1570                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2810073                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               7803626                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents               65                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1049469958                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3916326628                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3916321968                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              4660                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             672199888                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                377270070                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            5958245                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        5953011                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  72720727                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            187283500                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            75086036                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          17235466                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         11153184                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  806543834                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             6798395                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 700450406                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1593652                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       237057994                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    599635413                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved        3077315                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     462356637                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.514957                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.708817                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           192897981     41.72%     41.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            75235662     16.27%     57.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            69361266     15.00%     72.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            61039846     13.20%     86.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            35358169      7.65%     93.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15549191      3.36%     97.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             7530638      1.63%     98.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             4060857      0.88%     99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1323027      0.29%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       462356637                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  463542      4.68%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                6723177     67.88%     72.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2717455     27.44%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             472173393     67.41%     67.41% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               385744      0.06%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 178      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            162454570     23.19%     90.66% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            65436518      9.34%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              700450406                       # Type of FU issued
system.cpu.iq.rate                           1.502531                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     9904174                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014140                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1874754883                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1050459229                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    668042045                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 392                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                808                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              710354382                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     198                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          9116513                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     60510496                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        49356                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        63473                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     17482111                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        20858                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           384                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               38280378                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 2896329                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                176068                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           822095360                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           8083425                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             187283500                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             75086036                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            5309620                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  85965                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  9347                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          63473                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       10562567                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      7713138                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             18275705                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             681639675                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             155144326                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          18810731                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       8753131                       # number of nop insts executed
system.cpu.iew.exec_refs                    219063000                       # number of memory reference insts executed
system.cpu.iew.exec_branches                141943727                       # Number of branches executed
system.cpu.iew.exec_stores                   63918674                       # Number of stores executed
system.cpu.iew.exec_rate                     1.462180                       # Inst execution rate
system.cpu.iew.wb_sent                      672829860                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     668042061                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 381675027                       # num instructions producing a value
system.cpu.iew.wb_consumers                 656276447                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.433012                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.581577                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts      510298855                       # The number of committed instructions
system.cpu.commit.commitCommittedOps        574685416                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts       247426936                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         3721080                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          15423001                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    424076260                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.355146                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.070427                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    206251262     48.64%     48.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    102654685     24.21%     72.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     40133314      9.46%     82.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     19523005      4.60%     86.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     17475751      4.12%     91.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7238789      1.71%     92.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      7738360      1.82%     94.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3820773      0.90%     95.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     19240321      4.54%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    424076260                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            510298855                       # Number of instructions committed
system.cpu.commit.committedOps              574685416                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      184376929                       # Number of memory references committed
system.cpu.commit.loads                     126773004                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  120192189                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 473701493                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              19240321                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1226941153                       # The number of ROB reads
system.cpu.rob.rob_writes                  1682652305                       # The number of ROB writes
system.cpu.timesIdled                           99109                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         3823794                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   508954971                       # Number of Instructions Simulated
system.cpu.committedOps                     573341532                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             508954971                       # Number of Instructions Simulated
system.cpu.cpi                               0.915956                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.915956                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.091755                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.091755                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3162535433                       # number of integer regfile reads
system.cpu.int_regfile_writes               777163195                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads              1130648260                       # number of misc regfile reads
system.cpu.misc_regfile_writes                4463980                       # number of misc regfile writes
system.cpu.icache.replacements                  16198                       # number of replacements
system.cpu.icache.tagsinuse               1123.010204                       # Cycle average of tags in use
system.cpu.icache.total_refs                126921132                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  18053                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                7030.473162                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1123.010204                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.548345                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.548345                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    126921167                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       126921167                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     126921167                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        126921167                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    126921167                       # number of overall hits
system.cpu.icache.overall_hits::total       126921167                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        20144                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         20144                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        20144                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          20144                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        20144                       # number of overall misses
system.cpu.icache.overall_misses::total         20144                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    271671500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    271671500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    271671500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    271671500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    271671500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    271671500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    126941311                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    126941311                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    126941311                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    126941311                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    126941311                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    126941311                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000159                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000159                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000159                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13486.472399                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13486.472399                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13486.472399                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks            8                       # number of writebacks
system.cpu.icache.writebacks::total                 8                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1838                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1838                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1838                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1838                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1838                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1838                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18306                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        18306                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        18306                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        18306                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        18306                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        18306                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    173356500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    173356500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    173356500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    173356500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    173356500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    173356500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000144                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000144                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000144                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9469.927892                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9469.927892                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9469.927892                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1204660                       # number of replacements
system.cpu.dcache.tagsinuse               4052.912718                       # Cycle average of tags in use
system.cpu.dcache.total_refs                197226176                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1208756                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 163.164589                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             5518270000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4052.912718                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.989481                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.989481                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    139976270                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       139976270                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     52778956                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       52778956                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      2238371                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      2238371                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      2231989                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      2231989                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     192755226                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        192755226                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    192755226                       # number of overall hits
system.cpu.dcache.overall_hits::total       192755226                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1318997                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1318997                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1460350                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1460350                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           74                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           74                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2779347                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2779347                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2779347                       # number of overall misses
system.cpu.dcache.overall_misses::total       2779347                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  15287634500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  15287634500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  25192123491                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  25192123491                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       676500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       676500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  40479757991                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  40479757991                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  40479757991                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  40479757991                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    141295267                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    141295267                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2238445                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      2238445                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      2231989                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      2231989                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    195534573                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    195534573                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    195534573                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    195534573                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009335                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026924                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000033                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.014214                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.014214                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11590.348196                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17250.743651                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9141.891892                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14564.485108                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14564.485108                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       560500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              94                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets  5962.765957                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1073398                       # number of writebacks
system.cpu.dcache.writebacks::total           1073398                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       451124                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       451124                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1119210                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1119210                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           74                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           74                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1570334                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1570334                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1570334                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1570334                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       867873                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       867873                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       341140                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       341140                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1209013                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1209013                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1209013                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1209013                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6213938000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   6213938000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4372891497                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4372891497                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10586829497                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  10586829497                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10586829497                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10586829497                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006142                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006290                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006183                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006183                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7159.962345                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12818.466017                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8756.588636                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8756.588636                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                218347                       # number of replacements
system.cpu.l2cache.tagsinuse             20950.026820                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1558196                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                238767                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  6.526011                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          170531011000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 13687.762920                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    201.638936                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   7060.624965                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.417717                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.006154                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.215473                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.639344                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        14281                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       742482                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         756763                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1073406                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1073406                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data          203                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total          203                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       232563                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       232563                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        14281                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       975045                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          989326                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        14281                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       975045                       # number of overall hits
system.cpu.l2cache.overall_hits::total         989326                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3887                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       124728                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       128615                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           48                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           48                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       108968                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       108968                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3887                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       233696                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        237583                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3887                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       233696                       # number of overall misses
system.cpu.l2cache.overall_misses::total       237583                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    133254500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   4265335000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   4398589500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       411500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       411500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3731222000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   3731222000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    133254500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7996557000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8129811500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    133254500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7996557000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8129811500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        18168                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       867210                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       885378                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1073406                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1073406                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          251                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          251                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       341531                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       341531                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        18168                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1208741                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1226909                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        18168                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1208741                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1226909                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.213948                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.143827                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.191235                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.319057                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.213948                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.193338                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.213948                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.193338                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34282.094160                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34197.092874                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  8572.916667                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34241.447030                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34282.094160                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34217.774374                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34282.094160                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34217.774374                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       170975                       # number of writebacks
system.cpu.l2cache.writebacks::total           170975                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           25                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           30                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           25                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           30                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           25                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           30                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3882                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       124703                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       128585                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           48                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           48                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       108968                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       108968                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3882                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       233671                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       237553                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3882                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       233671                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       237553                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    120642000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   3870272500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3990914500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1489500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1489500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3378939500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3378939500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    120642000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7249212000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   7369854000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    120642000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7249212000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   7369854000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.213672                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.143798                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.191235                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.319057                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.213672                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.193318                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.213672                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.193318                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31077.279753                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.921349                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31031.250000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.548381                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31077.279753                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31023.156489                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31077.279753                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31023.156489                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------