1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.233382 # Number of seconds simulated
sim_ticks 233381523500 # Number of ticks simulated
final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 139639 # Simulator instruction rate (inst/s)
host_op_rate 151279 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 64502789 # Simulator tick rate (ticks/s)
host_mem_usage 317896 # Number of bytes of host memory used
host_seconds 3618.16 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 547350944 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 689856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9181056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 16498240 # Number of bytes read from this memory
system.physmem.bytes_read::total 26369152 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 689856 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 689856 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18710272 # Number of bytes written to this memory
system.physmem.bytes_written::total 18710272 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 10779 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 143454 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 257785 # Number of read requests responded to by this memory
system.physmem.num_reads::total 412018 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 292348 # Number of write requests responded to by this memory
system.physmem.num_writes::total 292348 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 2955915 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 39339258 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 70692143 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 112987316 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 2955915 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 2955915 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 80170322 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 80170322 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 80170322 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 2955915 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 39339258 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 70692143 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 193157639 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 412018 # Number of read requests accepted
system.physmem.writeReqs 292348 # Number of write requests accepted
system.physmem.readBursts 412018 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 292348 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 26233536 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 135616 # Total number of bytes read from write queue
system.physmem.bytesWritten 18708736 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 26369152 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 18710272 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 2119 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 26413 # Per bank write bursts
system.physmem.perBankRdBursts::1 25441 # Per bank write bursts
system.physmem.perBankRdBursts::2 25280 # Per bank write bursts
system.physmem.perBankRdBursts::3 24861 # Per bank write bursts
system.physmem.perBankRdBursts::4 26943 # Per bank write bursts
system.physmem.perBankRdBursts::5 26409 # Per bank write bursts
system.physmem.perBankRdBursts::6 25350 # Per bank write bursts
system.physmem.perBankRdBursts::7 24226 # Per bank write bursts
system.physmem.perBankRdBursts::8 25719 # Per bank write bursts
system.physmem.perBankRdBursts::9 24800 # Per bank write bursts
system.physmem.perBankRdBursts::10 25359 # Per bank write bursts
system.physmem.perBankRdBursts::11 26216 # Per bank write bursts
system.physmem.perBankRdBursts::12 26433 # Per bank write bursts
system.physmem.perBankRdBursts::13 25856 # Per bank write bursts
system.physmem.perBankRdBursts::14 25009 # Per bank write bursts
system.physmem.perBankRdBursts::15 25584 # Per bank write bursts
system.physmem.perBankWrBursts::0 18684 # Per bank write bursts
system.physmem.perBankWrBursts::1 18331 # Per bank write bursts
system.physmem.perBankWrBursts::2 18001 # Per bank write bursts
system.physmem.perBankWrBursts::3 18053 # Per bank write bursts
system.physmem.perBankWrBursts::4 18581 # Per bank write bursts
system.physmem.perBankWrBursts::5 18287 # Per bank write bursts
system.physmem.perBankWrBursts::6 18028 # Per bank write bursts
system.physmem.perBankWrBursts::7 17667 # Per bank write bursts
system.physmem.perBankWrBursts::8 18026 # Per bank write bursts
system.physmem.perBankWrBursts::9 17689 # Per bank write bursts
system.physmem.perBankWrBursts::10 18246 # Per bank write bursts
system.physmem.perBankWrBursts::11 18799 # Per bank write bursts
system.physmem.perBankWrBursts::12 18831 # Per bank write bursts
system.physmem.perBankWrBursts::13 18312 # Per bank write bursts
system.physmem.perBankWrBursts::14 18349 # Per bank write bursts
system.physmem.perBankWrBursts::15 18440 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 233381437000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 412018 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 292348 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 312437 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 47937 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 13197 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9328 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7381 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 5333 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 4454 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3421 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 72 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 6242 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 6513 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 15344 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 16357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 16904 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 17203 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 17602 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 17794 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 18042 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 18396 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 18527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 18799 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 19969 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 18456 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 17828 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 307121 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 146.330964 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 102.916756 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 182.072957 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 184589 60.10% 60.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 81854 26.65% 86.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 16654 5.42% 92.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 7226 2.35% 94.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 4782 1.56% 96.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2270 0.74% 96.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1753 0.57% 97.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1588 0.52% 97.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6405 2.09% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 307121 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 17353 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.620930 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 116.705820 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 17352 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 17353 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 17353 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.845733 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.805125 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.212117 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 10719 61.77% 61.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 285 1.64% 63.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 5449 31.40% 94.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 585 3.37% 98.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 128 0.74% 98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 65 0.37% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 37 0.21% 99.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 35 0.20% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 29 0.17% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 15 0.09% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 4 0.02% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 17353 # Writes before turning the bus around for reads
system.physmem.totQLat 9387910450 # Total ticks spent queuing
system.physmem.totMemAccLat 17073516700 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2049495000 # Total ticks spent in databus transfers
system.physmem.avgQLat 22902.98 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 41652.98 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 112.41 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 112.99 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 80.17 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.50 # Data bus utilization in percentage
system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
system.physmem.avgWrQLen 21.73 # Average write queue length when enqueuing
system.physmem.readRowHits 299659 # Number of row buffer hits during reads
system.physmem.writeRowHits 95432 # Number of row buffer hits during writes
system.physmem.readRowHitRate 73.11 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 32.64 # Row buffer hit rate for writes
system.physmem.avgGap 331335.47 # Average gap between requests
system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1156453200 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 631001250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1598134200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 943500960 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 74948893020 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 74281875750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 168802927260 # Total energy per rank (pJ)
system.physmem_0.averagePower 723.304109 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 123045424463 # Time in different power states
system.physmem_0.memoryStateTime::REF 7792980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 102539140537 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 1165048920 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 635691375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1598610000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 950447520 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 74482095510 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 74691339000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 168766301205 # Total energy per rank (pJ)
system.physmem_1.averagePower 723.147212 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 123736015873 # Time in different power states
system.physmem_1.memoryStateTime::REF 7792980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 101848756127 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 175093442 # Number of BP lookups
system.cpu.branchPred.condPredicted 131339013 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 7445255 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 90524838 # Number of BTB lookups
system.cpu.branchPred.BTBHits 83882931 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 92.662890 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 12110656 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 104163 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 466763048 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 7833738 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 731827371 # Number of instructions fetch has processed
system.cpu.fetch.Branches 175093442 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 95993587 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 450556948 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 14942959 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 6375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 162 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 12684 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 236728618 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 34396 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 465881386 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.701216 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.179605 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 93942381 20.16% 20.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 132696529 28.48% 48.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 57859169 12.42% 61.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 181383307 38.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 465881386 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.375123 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.567878 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 32362328 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 117422213 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 287082190 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 22031979 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 6982676 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 24051776 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 496598 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 715820836 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 30011268 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 6982676 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 63423410 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 54356901 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 40333857 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 276674345 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 24110197 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 686603373 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 13342977 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 9430232 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2385222 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1668168 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 1866322 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 831029947 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 3019214336 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 723928049 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 176906196 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1534779 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 42310456 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 143529227 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 67980457 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 12876117 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11223865 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 668168633 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 610244720 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5860928 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 122748160 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 319249921 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 465881386 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.309871 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.101485 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 148726725 31.92% 31.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 101219272 21.73% 53.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 145704053 31.27% 84.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 63308472 13.59% 98.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 6922394 1.49% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 465881386 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 71926892 52.97% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 44548808 32.81% 85.78% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 19308609 14.22% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 413151205 67.70% 67.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 351762 0.06% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 134213175 21.99% 89.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 62528575 10.25% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 610244720 # Type of FU issued
system.cpu.iq.rate 1.307397 # Inst issue rate
system.cpu.iq.fu_busy_cnt 135784339 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.222508 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 1828015800 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 793923222 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 594984495 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 746028882 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 7272735 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 27644471 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 25523 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 28862 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 11119980 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 225173 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 19543 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 6982676 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 23041794 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 922625 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 672634659 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 143529227 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 67980457 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1489791 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 257738 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 528673 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 28862 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3822612 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3731799 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 7554411 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 599400407 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 129575642 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10844313 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 1487693 # number of nop insts executed
system.cpu.iew.exec_refs 190530493 # number of memory reference insts executed
system.cpu.iew.exec_branches 131374378 # Number of branches executed
system.cpu.iew.exec_stores 60954851 # Number of stores executed
system.cpu.iew.exec_rate 1.284164 # Inst execution rate
system.cpu.iew.wb_sent 596279757 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 594984511 # cumulative count of insts written-back
system.cpu.iew.wb_producers 349915362 # num instructions producing a value
system.cpu.iew.wb_consumers 570660996 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.274704 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.613176 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 110032490 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 6956452 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 448764802 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.222678 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.888107 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 219732753 48.96% 48.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 116339584 25.92% 74.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 43745322 9.75% 84.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 23276938 5.19% 89.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 11568250 2.58% 92.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 7761637 1.73% 94.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8261110 1.84% 95.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 4247723 0.95% 96.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 13831485 3.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 448764802 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 172745233 # Number of memory references committed
system.cpu.commit.loads 115884756 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
system.cpu.commit.branches 121548301 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 448454354 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction
system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1093653497 # The number of ROB reads
system.cpu.rob.rob_writes 1334601058 # The number of ROB writes
system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 881662 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.923848 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.923848 # CPI: Total CPI of All Threads
system.cpu.ipc 1.082429 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.082429 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 611089137 # number of integer regfile reads
system.cpu.int_regfile_writes 328121807 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.cc_regfile_reads 2170187431 # number of cc regfile reads
system.cpu.cc_regfile_writes 376547848 # number of cc regfile writes
system.cpu.misc_regfile_reads 217970630 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
system.cpu.dcache.tags.replacements 2821443 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.630682 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 169417803 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2821955 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 60.035615 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 498977500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.630682 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999279 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 356251797 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 356251797 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 114676407 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114676407 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 51761464 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 51761464 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 166437871 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 166437871 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 166440653 # number of overall hits
system.cpu.dcache.overall_hits::total 166440653 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 4819248 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 4819248 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2477842 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2477842 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 7297090 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7297090 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7297102 # number of overall misses
system.cpu.dcache.overall_misses::total 7297102 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 56184151983 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 56184151983 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18816988488 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 18816988488 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1349500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 1349500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 75001140471 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 75001140471 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 75001140471 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 75001140471 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 119495655 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 119495655 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2794 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2794 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 173734961 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 173734961 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 173737755 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 173737755 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040330 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040330 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045684 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.045684 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004295 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.004295 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.042001 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.042001 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.042001 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.042001 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11658.281952 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11658.281952 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7594.103453 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 7594.103453 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20446.969697 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20446.969697 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10278.226042 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10278.226042 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10278.209140 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10278.209140 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 705176 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 220270 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 3.201416 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2356074 # number of writebacks
system.cpu.dcache.writebacks::total 2356074 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2516883 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2516883 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1958234 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 1958234 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4475117 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4475117 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4475117 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4475117 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2302365 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 2302365 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519608 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 519608 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2821973 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2821973 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2821983 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2821983 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27555148045 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27555148045 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4324407514 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4324407514 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 652250 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 652250 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31879555559 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 31879555559 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31880207809 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 31880207809 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019267 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019267 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003579 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003579 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016243 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.016243 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11968.192726 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11968.192726 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8322.442137 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8322.442137 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65225 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65225 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11296.903110 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11296.903110 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11297.094210 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11297.094210 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 73466 # number of replacements
system.cpu.icache.tags.tagsinuse 466.200525 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 236646541 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 73978 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 3198.877247 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 115003506250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 466.200525 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.910548 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.910548 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 15 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 473531001 # Number of tag accesses
system.cpu.icache.tags.data_accesses 473531001 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 236646541 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 236646541 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 236646541 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 236646541 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 236646541 # number of overall hits
system.cpu.icache.overall_hits::total 236646541 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 81956 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 81956 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 81956 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 81956 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 81956 # number of overall misses
system.cpu.icache.overall_misses::total 81956 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1579166787 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1579166787 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1579166787 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1579166787 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1579166787 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1579166787 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 236728497 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 236728497 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 236728497 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 236728497 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 236728497 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 236728497 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19268.470728 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19268.470728 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19268.470728 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19268.470728 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 192617 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 91 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 6539 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 29.456645 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7948 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 7948 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 7948 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 7948 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 7948 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 7948 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74008 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 74008 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 74008 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 74008 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 74008 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 74008 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1251050514 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1251050514 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1251050514 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1251050514 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1251050514 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1251050514 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16904.260539 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16904.260539 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued 8510841 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 8513336 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 1033 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 743496 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 401010 # number of replacements
system.cpu.l2cache.tags.tagsinuse 15417.841274 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4560227 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 417347 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 10.926704 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 34597011000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 8457.509015 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 475.097428 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 4918.264697 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1566.970133 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.516205 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028998 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.300187 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095640 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.941030 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 1096 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15241 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 254 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 810 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1567 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9927 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3395 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066895 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930237 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 84971798 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 84971798 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 63191 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 2156048 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2219239 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2356074 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2356074 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 516713 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 516713 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 63191 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2672761 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2735952 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 63191 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2672761 # number of overall hits
system.cpu.l2cache.overall_hits::total 2735952 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 10784 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 143994 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 154778 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 5200 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 5200 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 10784 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 149194 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 159978 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 10784 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 149194 # number of overall misses
system.cpu.l2cache.overall_misses::total 159978 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 802172675 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11140653266 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 11942825941 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 468295272 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 468295272 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 802172675 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11608948538 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 12411121213 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 802172675 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11608948538 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 12411121213 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 73975 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 2300042 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2374017 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2356074 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2356074 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 521913 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 521913 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 73975 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2821955 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2895930 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 73975 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2821955 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2895930 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.145779 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062605 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.065197 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.071429 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.071429 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009963 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.009963 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.145779 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.052869 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.055242 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.145779 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.052869 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.055242 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74385.448349 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77368.871384 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.004413 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90056.783077 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90056.783077 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74385.448349 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77811.095205 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77580.174855 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74385.448349 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77811.095205 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77580.174855 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 292348 # number of writebacks
system.cpu.l2cache.writebacks::total 292348 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4205 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 4209 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1534 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 1534 # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 5739 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 5743 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 5739 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 5743 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10780 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 139789 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 150569 # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275622 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 275622 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3666 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3666 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10780 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143455 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 154235 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10780 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143455 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275622 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 429857 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 710057825 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9596193047 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10306250872 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18910984010 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 283384780 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 283384780 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 710057825 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9879577827 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 10589635652 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 710057825 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9879577827 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 29500619662 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060777 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063424 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.071429 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.071429 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007024 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007024 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.053259 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.148435 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65868.072820 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68647.697938 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68448.690448 # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 68612.026652 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77300.812875 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77300.812875 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68659.095873 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68628.915342 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2374050 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2374049 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2356074 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 317604 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 521913 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 521913 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147982 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8000040 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8148022 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734336 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331393856 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 336128192 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 317637 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 5569669 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.057024 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.231888 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 5252065 94.30% 94.30% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 317604 5.70% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 5569669 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4982106500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 112829788 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 4256050685 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
system.membus.trans_dist::ReadReq 408353 # Transaction distribution
system.membus.trans_dist::ReadResp 408353 # Transaction distribution
system.membus.trans_dist::Writeback 292348 # Transaction distribution
system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
system.membus.trans_dist::ReadExReq 3665 # Transaction distribution
system.membus.trans_dist::ReadExResp 3665 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1116390 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1116390 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45079424 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 45079424 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 704369 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 704369 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 704369 # Request fanout histogram
system.membus.reqLayer0.occupancy 2100254662 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.membus.respLayer1.occupancy 2178151058 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------
|