path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.234001                       # Number of seconds simulated
sim_ticks                                234001297000                       # Number of ticks simulated
final_tick                               234001297000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 134504                       # Simulator instruction rate (inst/s)
host_op_rate                                   145716                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               62295833                       # Simulator tick rate (ticks/s)
host_mem_usage                                 343376                       # Number of bytes of host memory used
host_seconds                                  3756.29                       # Real time elapsed on the host
sim_insts                                   505237724                       # Number of instructions simulated
sim_ops                                     547350945                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            517504                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10131008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     16480064                       # Number of bytes read from this memory
system.physmem.bytes_read::total             27128576                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       517504                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          517504                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18730688                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18730688                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               8086                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             158297                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       257501                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                423884                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          292667                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               292667                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              2211543                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             43294666                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     70427234                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               115933443                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2211543                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2211543                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          80045232                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               80045232                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          80045232                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2211543                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            43294666                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     70427234                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              195978674                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        423884                       # Number of read requests accepted
system.physmem.writeReqs                       292667                       # Number of write requests accepted
system.physmem.readBursts                      423884                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     292667                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26972992                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    155584                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18728832                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  27128576                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18730688                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     2431                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs          98651                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               26584                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25337                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25274                       # Per bank write bursts
system.physmem.perBankRdBursts::3               32197                       # Per bank write bursts
system.physmem.perBankRdBursts::4               27335                       # Per bank write bursts
system.physmem.perBankRdBursts::5               28299                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25126                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24198                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25368                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25926                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25318                       # Per bank write bursts
system.physmem.perBankRdBursts::11              26278                       # Per bank write bursts
system.physmem.perBankRdBursts::12              27572                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25872                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25056                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25713                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18662                       # Per bank write bursts
system.physmem.perBankWrBursts::1               18231                       # Per bank write bursts
system.physmem.perBankWrBursts::2               18003                       # Per bank write bursts
system.physmem.perBankWrBursts::3               17875                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18721                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18310                       # Per bank write bursts
system.physmem.perBankWrBursts::6               17836                       # Per bank write bursts
system.physmem.perBankWrBursts::7               17744                       # Per bank write bursts
system.physmem.perBankWrBursts::8               17983                       # Per bank write bursts
system.physmem.perBankWrBursts::9               17940                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18239                       # Per bank write bursts
system.physmem.perBankWrBursts::11              18938                       # Per bank write bursts
system.physmem.perBankWrBursts::12              18976                       # Per bank write bursts
system.physmem.perBankWrBursts::13              18211                       # Per bank write bursts
system.physmem.perBankWrBursts::14              18390                       # Per bank write bursts
system.physmem.perBankWrBursts::15              18579                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    234001244500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  423884                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 292667                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    323806                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     49376                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     12876                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8979                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6144                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5227                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4284                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3341                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        70                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       29                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     7238                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     7730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    12413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    15049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    16333                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    16979                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17275                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17603                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17899                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    18115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    18307                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    18692                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    18718                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    18910                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    19072                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17647                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17263                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17149                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      141                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       47                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       322061                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      141.901068                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      99.764285                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     180.057081                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         202493     62.87%     62.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        79759     24.77%     87.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        15144      4.70%     92.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7279      2.26%     94.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         4961      1.54%     96.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2580      0.80%     96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1828      0.57%     97.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1538      0.48%     97.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         6479      2.01%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         322061                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17076                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.676095                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      143.384257                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          17074     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::18432-19455            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17076                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17076                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.137386                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.076722                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.519222                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               9254     54.19%     54.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                359      2.10%     56.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               5270     30.86%     87.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               1365      7.99%     95.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                405      2.37%     97.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                163      0.95%     98.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                106      0.62%     99.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 62      0.36%     99.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 41      0.24%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 19      0.11%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 11      0.06%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  5      0.03%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  3      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  3      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  3      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  2      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                  1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17076                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8693371575                       # Total ticks spent queuing
system.physmem.totMemAccLat               16595615325                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2107265000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20627.14                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  39377.14                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         115.27                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          80.04                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      115.93                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       80.05                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.53                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.90                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.63                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.60                       # Average write queue length when enqueuing
system.physmem.readRowHits                     306420                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     85606                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   72.71                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  29.25                       # Row buffer hit rate for writes
system.physmem.avgGap                       326566.07                       # Average gap between requests
system.physmem.pageHitRate                      54.90                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1224553680                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  668159250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1671883200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                942075360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            15283753680                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            82043634285                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            68432158500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             170266217955                       # Total energy per rank (pJ)
system.physmem_0.averagePower              727.632069                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   113312610225                       # Time in different power states
system.physmem_0.memoryStateTime::REF      7813780000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    112874154775                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1210227480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  660342375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1615325400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                954218880                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            15283753680                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            79914700530                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            70299646500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             169938214845                       # Total energy per rank (pJ)
system.physmem_1.averagePower              726.230337                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   116426727240                       # Time in different power states
system.physmem_1.memoryStateTime::REF      7813780000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    109759940510                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               175128597                       # Number of BP lookups
system.cpu.branchPred.condPredicted         131371974                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           7444955                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             90537565                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                83893856                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             92.661931                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                12111370                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             104180                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        468002595                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            7807530                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      731939592                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   175128597                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           96005226                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     452073756                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                14942657                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 4553                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           179                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        11657                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 236761982                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 33954                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          467369003                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.696062                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.181505                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 95368751     20.41%     20.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                132719598     28.40%     48.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 57874720     12.38%     61.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                181405934     38.81%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            467369003                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.374204                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.563965                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32359971                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             118993599                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 286955454                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              22077159                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                6982820                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             24051378                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                496211                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              715838012                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              30014698                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                6982820                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 63444256                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                55810223                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       40372652                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 276569326                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              24189726                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              686622974                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              13340540                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               9445783                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2386683                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1668073                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1901045                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           831058832                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3019300335                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        723953090                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               416                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             654123751                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                176935081                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1544712                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        1535132                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  42423418                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            143529755                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            67982396                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          12868793                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         11217167                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  668185878                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2978339                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 610253474                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           5862945                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       123813272                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    319307246                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            707                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     467369003                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.305721                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.102066                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           150209828     32.14%     32.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           101164226     21.65%     53.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           145806231     31.20%     84.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            63278562     13.54%     98.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6909680      1.48%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 476      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       467369003                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                71905667     52.96%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     30      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.96% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               44557603     32.82%     85.78% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              19305643     14.22%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             413150420     67.70%     67.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               351795      0.06%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            134216313     21.99%     89.75% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            62534943     10.25%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              610253474                       # Type of FU issued
system.cpu.iq.rate                           1.303953                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   135768943                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.222480                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1829507546                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         795005708                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    594983942                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 293                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                316                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              746022240                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     177                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          7274295                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     27644999                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        25509                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        28969                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     11121919                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       225058                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         22341                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                6982820                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                22939909                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                921157                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           672651686                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             143529755                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             67982396                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1489797                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 258383                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                526747                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          28969                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3822799                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3731713                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              7554512                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             599398028                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             129575309                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10855446                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1487469                       # number of nop insts executed
system.cpu.iew.exec_refs                    190532110                       # number of memory reference insts executed
system.cpu.iew.exec_branches                131373386                       # Number of branches executed
system.cpu.iew.exec_stores                   60956801                       # Number of stores executed
system.cpu.iew.exec_rate                     1.280758                       # Inst execution rate
system.cpu.iew.wb_sent                      596278477                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     594983958                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 349895185                       # num instructions producing a value
system.cpu.iew.wb_consumers                 570621697                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.271326                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.613182                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       110038028                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           6956447                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    450252376                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.218638                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.886273                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    221217275     49.13%     49.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    116327442     25.84%     74.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     43752953      9.72%     84.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     23318372      5.18%     89.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     11527046      2.56%     92.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7779334      1.73%     94.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      8252081      1.83%     95.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      4233959      0.94%     96.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     13843914      3.07%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    450252376                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            506581608                       # Number of instructions committed
system.cpu.commit.committedOps              548694829                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      172745233                       # Number of memory references committed
system.cpu.commit.loads                     115884756                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  121548302                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 448454354                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        375610374     68.46%     68.46% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          339219      0.06%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       115884756     21.12%     89.64% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       56860477     10.36%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         548694829                       # Class of committed instruction
system.cpu.commit.bw_lim_events              13843914                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1095134181                       # The number of ROB reads
system.cpu.rob.rob_writes                  1334612111                       # The number of ROB writes
system.cpu.timesIdled                           12504                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          633592                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   505237724                       # Number of Instructions Simulated
system.cpu.committedOps                     547350945                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.926302                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.926302                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.079562                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.079562                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                611088799                       # number of integer regfile reads
system.cpu.int_regfile_writes               328120173                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.cc_regfile_reads                2170182732                       # number of cc regfile reads
system.cpu.cc_regfile_writes                376542810                       # number of cc regfile writes
system.cpu.misc_regfile_reads               217972310                       # number of misc regfile reads
system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2820726                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.629844                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           169352944                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2821238                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             60.027883                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         500883000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.629844                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999277                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999277                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          164                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          281                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         356245422                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        356245422                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    114648159                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114648159                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     51724842                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       51724842                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2783                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2783                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488558                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488558                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     166373001                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        166373001                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    166375784                       # number of overall hits
system.cpu.dcache.overall_hits::total       166375784                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      4844666                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       4844666                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2514464                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2514464                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           67                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           67                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      7359130                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        7359130                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      7359142                       # number of overall misses
system.cpu.dcache.overall_misses::total       7359142                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  57569719500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  57569719500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  18925127941                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  18925127941                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       941000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       941000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  76494847441                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  76494847441                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  76494847441                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  76494847441                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    119492825                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    119492825                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2795                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2795                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488625                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488625                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    173732131                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    173732131                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    173734926                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    173734926                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040544                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.040544                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046359                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.046359                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004293                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.004293                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000045                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000045                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.042359                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.042359                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.042358                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.042358                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11883.114233                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11883.114233                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7526.505824                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  7526.505824                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10394.550367                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10394.550367                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10394.533417                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10394.533417                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           17                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       905651                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          221227                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.500000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     4.093763                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2820726                       # number of writebacks
system.cpu.dcache.writebacks::total           2820726                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2542974                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      2542974                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1994900                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1994900                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           67                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           67                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4537874                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4537874                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4537874                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4537874                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2301692                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      2301692                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519564                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       519564                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2821256                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2821256                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2821266                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2821266                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29568664500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  29568664500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4603651495                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4603651495                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       644000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       644000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  34172315995                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  34172315995                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  34172959995                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  34172959995                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019262                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019262                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009579                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009579                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003578                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003578                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016239                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016239                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016239                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.016239                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12846.490538                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12846.490538                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8860.605229                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8860.605229                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        64400                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        64400                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.447787                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.447787                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.633121                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.633121                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             73505                       # number of replacements
system.cpu.icache.tags.tagsinuse           466.324466                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           236680067                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             74017                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           3197.644690                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      115567558500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   466.324466                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.910790                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.910790                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          257                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          120                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           19                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           16                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         473597840                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        473597840                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    236680067                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       236680067                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     236680067                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        236680067                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    236680067                       # number of overall hits
system.cpu.icache.overall_hits::total       236680067                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        81831                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         81831                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        81831                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          81831                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        81831                       # number of overall misses
system.cpu.icache.overall_misses::total         81831                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1321953198                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1321953198                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1321953198                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1321953198                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1321953198                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1321953198                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    236761898                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    236761898                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    236761898                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    236761898                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    236761898                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    236761898                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000346                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000346                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000346                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000346                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000346                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000346                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16154.674854                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16154.674854                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16154.674854                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16154.674854                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16154.674854                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16154.674854                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       160057                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          121                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              6454                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    24.799659                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    24.200000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        73505                       # number of writebacks
system.cpu.icache.writebacks::total             73505                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7785                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         7785                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         7785                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         7785                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         7785                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         7785                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        74046                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        74046                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        74046                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        74046                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        74046                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        74046                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1096634301                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1096634301                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1096634301                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1096634301                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1096634301                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1096634301                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000313                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000313                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000313                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14810.176120                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14810.176120                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14810.176120                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14810.176120                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14810.176120                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14810.176120                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued      8513868                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      8515266                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit          405                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage       743582                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           395654                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        15130.862056                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3181572                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           411591                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             7.729936                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     170394344500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 13787.674482                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data     0.001651                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1343.185923                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.841533                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.081982                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.923515                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022         1035                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        14902                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           39                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3          218                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4          778                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          154                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4872                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6295                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3370                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.063171                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909546                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         94911547                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        94911547                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      2356600                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      2356600                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       513929                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       513929                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       516839                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       516839                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        65920                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        65920                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2140480                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      2140480                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        65920                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2657319                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2723239                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        65920                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2657319                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2723239                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           28                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           28                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         5118                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         5118                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         8094                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         8094                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       158801                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       158801                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         8094                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       163919                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        172013                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         8094                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       163919                       # number of overall misses
system.cpu.l2cache.overall_misses::total       172013                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        69500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        69500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    486926500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    486926500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    587769500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    587769500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  12091050000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  12091050000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    587769500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12577976500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13165746000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    587769500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12577976500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13165746000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      2356600                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      2356600                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       513929                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       513929                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           28                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           28                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       521957                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       521957                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        74014                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        74014                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2299281                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      2299281                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        74014                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2821238                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2895252                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        74014                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2821238                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2895252                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009805                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.009805                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.109358                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.109358                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.069066                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.069066                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.109358                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.058102                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.059412                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.109358                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.058102                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.059412                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  2482.142857                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  2482.142857                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95139.996092                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95139.996092                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72617.926859                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72617.926859                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76139.633881                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76139.633881                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72617.926859                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76732.877214                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76539.249940                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72617.926859                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76732.877214                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76539.249940                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       292667                       # number of writebacks
system.cpu.l2cache.writebacks::total           292667                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1428                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         1428                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            7                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            7                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4193                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4193                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            7                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         5621                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         5628                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            7                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         5621                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         5628                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       350851                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       350851                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           28                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           28                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3690                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         3690                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         8087                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         8087                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       154608                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       154608                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         8087                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       158298                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       166385                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         8087                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       158298                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       350851                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       517236                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18662693863                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18662693863                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       481000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       481000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    335947000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    335947000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    538896500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    538896500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  10864639500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  10864639500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    538896500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11200586500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11739483000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    538896500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11200586500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18662693863                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  30402176863                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007070                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007070                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.109263                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.109263                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.067242                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.067242                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.109263                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056109                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.057468                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.109263                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056109                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.178650                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53192.648341                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17178.571429                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17178.571429                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91042.547425                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91042.547425                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66637.380982                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66637.380982                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70272.168969                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70272.168969                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66637.380982                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70756.336151                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70556.137873                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66637.380982                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70756.336151                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58778.153228                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5789543                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2894272                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23735                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops       260412                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops       244232                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        16180                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp       2373325                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      2649267                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       513929                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       265680                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       392283                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           28                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           28                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       521957                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       521957                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        74046                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      2299281                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       220710                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8440410                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8661120                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9386496                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    359623424                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          369009920                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      950663                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3845942                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.078099                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.283574                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3561756     92.61%     92.61% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             268006      6.97%     99.58% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2              16180      0.42%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3845942                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5789002505                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy         1506                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     111143345                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    4231890461                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             420198                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       292667                       # Transaction distribution
system.membus.trans_dist::CleanEvict            98618                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               33                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              33                       # Transaction distribution
system.membus.trans_dist::ReadExReq              3685                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3685                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        420199                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1239118                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1239118                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45859200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                45859200                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            815202                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  815202    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              815202                       # Request fanout histogram
system.membus.reqLayer0.occupancy          2212929834                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2242544064                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------