path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.233457                       # Number of seconds simulated
sim_ticks                                233457400500                       # Number of ticks simulated
final_tick                               233457400500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 105147                       # Simulator instruction rate (inst/s)
host_op_rate                                   113911                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               48585649                       # Simulator tick rate (ticks/s)
host_mem_usage                                 312624                       # Number of bytes of host memory used
host_seconds                                  4805.07                       # Real time elapsed on the host
sim_insts                                   505237724                       # Number of instructions simulated
sim_ops                                     547350945                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            691264                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9218304                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     16465984                       # Number of bytes read from this memory
system.physmem.bytes_read::total             26375552                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       691264                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          691264                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18705216                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18705216                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst              10801                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144036                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       257281                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                412118                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          292269                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               292269                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              2960986                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             39486022                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     70531000                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               112978008                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2960986                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2960986                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          80122609                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               80122609                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          80122609                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2960986                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            39486022                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     70531000                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              193100617                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        412118                       # Number of read requests accepted
system.physmem.writeReqs                       292269                       # Number of write requests accepted
system.physmem.readBursts                      412118                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     292269                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26236672                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    138880                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18703040                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  26375552                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18705216                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     2170                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              3                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               26483                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25520                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25375                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24791                       # Per bank write bursts
system.physmem.perBankRdBursts::4               27157                       # Per bank write bursts
system.physmem.perBankRdBursts::5               26569                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25228                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24398                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25772                       # Per bank write bursts
system.physmem.perBankRdBursts::9               24727                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25014                       # Per bank write bursts
system.physmem.perBankRdBursts::11              25991                       # Per bank write bursts
system.physmem.perBankRdBursts::12              26422                       # Per bank write bursts
system.physmem.perBankRdBursts::13              25825                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25184                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25492                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18766                       # Per bank write bursts
system.physmem.perBankWrBursts::1               18282                       # Per bank write bursts
system.physmem.perBankWrBursts::2               18016                       # Per bank write bursts
system.physmem.perBankWrBursts::3               18022                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18772                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18348                       # Per bank write bursts
system.physmem.perBankWrBursts::6               17902                       # Per bank write bursts
system.physmem.perBankWrBursts::7               17779                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18029                       # Per bank write bursts
system.physmem.perBankWrBursts::9               17785                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18061                       # Per bank write bursts
system.physmem.perBankWrBursts::11              18677                       # Per bank write bursts
system.physmem.perBankWrBursts::12              18741                       # Per bank write bursts
system.physmem.perBankWrBursts::13              18309                       # Per bank write bursts
system.physmem.perBankWrBursts::14              18406                       # Per bank write bursts
system.physmem.perBankWrBursts::15              18340                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    233457328000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  412118                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 292269                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    312558                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     47724                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     13293                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9298                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7441                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6251                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5340                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4463                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3424                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        80                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6182                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6474                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    13223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    15385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    16372                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    16921                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17398                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    17900                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    17983                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    18306                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    18464                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    18800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    19851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    18588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17526                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       306919                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      146.415804                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     102.989110                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     182.052610                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         184181     60.01%     60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        81968     26.71%     86.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        16622      5.42%     92.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7343      2.39%     94.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         4784      1.56%     96.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2292      0.75%     96.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1776      0.58%     97.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1536      0.50%     97.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         6417      2.09%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         306919                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17350                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        23.626628                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      116.525366                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           17349     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17350                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17350                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.843516                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.802727                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.214220                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              10753     61.98%     61.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                289      1.67%     63.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               5387     31.05%     94.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                614      3.54%     98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                106      0.61%     98.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 63      0.36%     99.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 46      0.27%     99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 45      0.26%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 29      0.17%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 12      0.07%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  6      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17350                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9548241731                       # Total ticks spent queuing
system.physmem.totMemAccLat               17234766731                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2049740000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       23291.35                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  42041.35                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         112.38                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          80.11                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      112.98                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       80.12                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.50                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.88                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.63                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.16                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.73                       # Average write queue length when enqueuing
system.physmem.readRowHits                     299652                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     95604                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   73.10                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  32.71                       # Row buffer hit rate for writes
system.physmem.avgGap                       331433.33                       # Average gap between requests
system.physmem.pageHitRate                      56.29                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1157927400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  631805625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1602907800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                945308880                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            15248154480                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            75190255245                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            74116872000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             168893231430                       # Total energy per rank (pJ)
system.physmem_0.averagePower              723.449687                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   122769601530                       # Time in different power states
system.physmem_0.memoryStateTime::REF      7795580000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    102890225970                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1162259280                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  634169250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1594382400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                948263760                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            15248154480                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            74130386985                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            75046581000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             168764197155                       # Total energy per rank (pJ)
system.physmem_1.averagePower              722.896972                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   124323822632                       # Time in different power states
system.physmem_1.memoryStateTime::REF      7795580000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    101336607368                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               175097732                       # Number of BP lookups
system.cpu.branchPred.condPredicted         131341907                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           7444118                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             90491460                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                83879546                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             92.693328                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                12111412                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             104155                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        466914802                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            7831702                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      731836126                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   175097732                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           95990958                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     450721779                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                14940955                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 5640                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           179                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        13551                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 236729658                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 34605                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          466043328                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.700638                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.179812                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 94098707     20.19%     20.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                132700679     28.47%     48.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 57861600     12.42%     61.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                181382342     38.92%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            466043328                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.375010                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.567387                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32400238                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             117626282                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 286962359                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              22072426                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                6982023                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             24050963                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                496269                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              715816443                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              29997814                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                6982023                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 63475472                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                54498348                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       40339589                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 276580199                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              24167697                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              686605984                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              13334781                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               9429797                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2386503                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1670701                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1903283                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           831017415                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3019232506                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        723934620                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               416                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             654123751                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                176893664                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1544707                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        1534925                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  42378773                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            143528821                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            67986057                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          12870746                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         11400164                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  668175203                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2978333                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 610240343                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           5850286                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       123802591                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    319329527                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            701                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     466043328                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.309407                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.101734                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           148928880     31.96%     31.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           101192205     21.71%     53.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           145640431     31.25%     84.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            63360456     13.60%     98.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6920872      1.49%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 484      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       466043328                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                71964986     53.01%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     30      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     53.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               44551194     32.82%     85.83% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              19229314     14.17%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             413153889     67.70%     67.70% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               351748      0.06%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            134217118     21.99%     89.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            62517585     10.24%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              610240343                       # Type of FU issued
system.cpu.iq.rate                           1.306963                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   135745524                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.222446                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1828119531                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         794984388                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    594979068                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 293                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                316                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              745985690                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     177                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          7282878                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     27644065                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        25657                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        28996                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     11125580                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       225352                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         19393                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                6982023                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                23078591                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                913703                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           672641346                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             143528821                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             67986057                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1489791                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 257861                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                519542                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          28996                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3822175                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3731272                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              7553447                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             599393385                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             129576774                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10846958                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1487810                       # number of nop insts executed
system.cpu.iew.exec_refs                    190521112                       # number of memory reference insts executed
system.cpu.iew.exec_branches                131377011                       # Number of branches executed
system.cpu.iew.exec_stores                   60944338                       # Number of stores executed
system.cpu.iew.exec_rate                     1.283732                       # Inst execution rate
system.cpu.iew.wb_sent                      596274130                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     594979084                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 349911288                       # num instructions producing a value
system.cpu.iew.wb_consumers                 570684699                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.274278                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.613143                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       110037784                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           6955664                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    448925828                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.222239                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.888253                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    219983984     49.00%     49.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    116251312     25.90%     74.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     43736792      9.74%     84.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     23204110      5.17%     89.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     11645207      2.59%     92.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7768175      1.73%     94.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      8255090      1.84%     95.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      4243904      0.95%     96.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     13837254      3.08%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    448925828                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            506581608                       # Number of instructions committed
system.cpu.commit.committedOps              548694829                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      172745233                       # Number of memory references committed
system.cpu.commit.loads                     115884756                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  121548302                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 448454354                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        375610374     68.46%     68.46% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          339219      0.06%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       115884756     21.12%     89.64% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       56860477     10.36%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         548694829                       # Class of committed instruction
system.cpu.commit.bw_lim_events              13837254                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1093814049                       # The number of ROB reads
system.cpu.rob.rob_writes                  1334612597                       # The number of ROB writes
system.cpu.timesIdled                           13893                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          871474                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   505237724                       # Number of Instructions Simulated
system.cpu.committedOps                     547350945                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.924149                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.924149                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.082077                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.082077                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                611066187                       # number of integer regfile reads
system.cpu.int_regfile_writes               328122868                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.cc_regfile_reads                2170174557                       # number of cc regfile reads
system.cpu.cc_regfile_writes                376546263                       # number of cc regfile writes
system.cpu.misc_regfile_reads               217961585                       # number of misc regfile reads
system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2821455                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.631544                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           169406374                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2821967                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             60.031309                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         498452500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.631544                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999280                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999280                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         356233951                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        356233951                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    114665404                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114665404                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     51761034                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       51761034                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2783                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2783                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488559                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488559                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     166426438                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        166426438                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    166429221                       # number of overall hits
system.cpu.dcache.overall_hits::total       166429221                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      4821321                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       4821321                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2478272                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2478272                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           66                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           66                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      7299593                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        7299593                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      7299605                       # number of overall misses
system.cpu.dcache.overall_misses::total       7299605                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  56428314397                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  56428314397                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  18848897160                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  18848897160                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1043750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      1043750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  75277211557                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  75277211557                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  75277211557                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  75277211557                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    119486725                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    119486725                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2795                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2795                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488625                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488625                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    173726031                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    173726031                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    173728826                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    173728826                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040350                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.040350                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.045691                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.045691                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004293                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.004293                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000044                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000044                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.042018                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.042018                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.042017                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.042017                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11703.911521                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11703.911521                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7605.661187                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  7605.661187                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15814.393939                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15814.393939                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10312.521747                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10312.521747                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10312.504794                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10312.504794                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           28                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       711137                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 3                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          220355                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.333333                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     3.227233                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2352760                       # number of writebacks
system.cpu.dcache.writebacks::total           2352760                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2518936                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      2518936                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1958671                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1958671                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           66                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           66                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4477607                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4477607                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4477607                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4477607                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2302385                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      2302385                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519601                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       519601                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2821986                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2821986                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2821996                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2821996                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27643726875                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  27643726875                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4325979851                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4325979851                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       667500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       667500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31969706726                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  31969706726                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31970374226                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  31970374226                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019269                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019269                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009580                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009580                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003578                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003578                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016244                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016244                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016244                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.016244                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12006.561403                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12006.561403                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8325.580303                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8325.580303                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        66750                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        66750                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11328.797069                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11328.797069                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11328.993459                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11328.993459                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             73478                       # number of replacements
system.cpu.icache.tags.tagsinuse           466.210203                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           236647479                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             73990                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           3198.371118                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      115019212250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   466.210203                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.910567                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.910567                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          102                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          256                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          119                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           19                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           16                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         473533098                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        473533098                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    236647479                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       236647479                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     236647479                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        236647479                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    236647479                       # number of overall hits
system.cpu.icache.overall_hits::total       236647479                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        82060                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         82060                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        82060                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          82060                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        82060                       # number of overall misses
system.cpu.icache.overall_misses::total         82060                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1575366023                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1575366023                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1575366023                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1575366023                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1575366023                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1575366023                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    236729539                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    236729539                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    236729539                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    236729539                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    236729539                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    236729539                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000347                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000347                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000347                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000347                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000347                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000347                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19197.733646                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19197.733646                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19197.733646                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19197.733646                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19197.733646                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19197.733646                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       189178                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           92                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              6697                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    28.248171                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           23                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         8039                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         8039                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         8039                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         8039                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         8039                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         8039                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        74021                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        74021                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        74021                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        74021                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        74021                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        74021                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1246042756                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1246042756                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1246042756                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1246042756                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1246042756                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1246042756                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000313                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000313                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000313                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000313                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16833.638508                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16833.638508                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16833.638508                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16833.638508                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16833.638508                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16833.638508                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued      8513000                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      8515433                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit          981                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage       743879                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           401084                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        15418.862546                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4557178                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           417421                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            10.917462                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      34596581000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  8463.110256                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   474.072074                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  4920.608759                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1561.071458                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.516547                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.028935                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.300330                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.095280                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.941093                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022         1053                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        15284                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           24                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3          261                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4          767                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          143                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          215                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1548                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        10003                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3375                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.064270                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.932861                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         84919237                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        84919237                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        63177                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      2155522                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2218699                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2352760                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2352760                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           27                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           27                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       516754                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       516754                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        63177                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2672276                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2735453                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        63177                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2672276                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2735453                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst        10810                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       144544                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       155354                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         5147                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         5147                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst        10810                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       149691                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        160501                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        10810                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       149691                       # number of overall misses
system.cpu.l2cache.overall_misses::total       160501                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    797246429                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11231476587                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  12028723016                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    470778109                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    470778109                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    797246429                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11702254696                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  12499501125                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    797246429                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11702254696                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  12499501125                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        73987                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      2300066                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2374053                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2352760                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2352760                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           29                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           29                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       521901                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       521901                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        73987                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2821967                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2895954                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        73987                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2821967                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2895954                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.146107                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.062843                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.065438                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.068966                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.068966                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009862                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.009862                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.146107                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.053045                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.055422                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.146107                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.053045                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.055422                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73750.825994                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77702.821196                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77427.829448                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91466.506509                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91466.506509                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73750.825994                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78176.074019                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77878.026461                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73750.825994                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78176.074019                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77878.026461                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       292269                       # number of writebacks
system.cpu.l2cache.writebacks::total           292269                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data         4161                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total         4169                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1493                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         1493                       # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         5654                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         5662                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         5654                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         5662                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10802                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       140383                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       151185                       # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       275132                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       275132                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3654                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         3654                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        10802                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       144037                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       154839                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        10802                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       144037                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       275132                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       429971                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    704756821                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   9683951989                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10388708810                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18994026058                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18994026058                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        28002                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        28002                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    285290758                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    285290758                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    704756821                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9969242747                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  10673999568                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    704756821                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9969242747                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18994026058                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  29668025626                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.145999                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.061034                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.063682                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.068966                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.068966                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007001                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007001                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.145999                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.051041                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.053467                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.145999                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.051041                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.148473                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65243.179133                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68982.369582                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68715.208586                       # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69036.048362                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78076.288451                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78076.288451                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65243.179133                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69213.068496                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68936.117955                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65243.179133                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69213.068496                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69036.048362                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69000.061925                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        2374087                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       2374086                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      2352760                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       317092                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           29                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           29                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       521901                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       521901                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       148007                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7996752                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8144759                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4735104                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    331182528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          335917632                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      317126                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      5565869                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.056971                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.231787                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            5248777     94.30%     94.30% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4             317092      5.70%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5565869                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4977148500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     112866029                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    4256213768                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
system.membus.trans_dist::ReadReq              408465                       # Transaction distribution
system.membus.trans_dist::ReadResp             408465                       # Transaction distribution
system.membus.trans_dist::Writeback            292269                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               3                       # Transaction distribution
system.membus.trans_dist::ReadExReq              3653                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3653                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1116511                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1116511                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45080768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                45080768                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            704390                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  704390    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              704390                       # Request fanout histogram
system.membus.reqLayer0.occupancy          2099926272                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2178828981                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)

---------- End Simulation Statistics   ----------