path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.202425                       # Number of seconds simulated
sim_ticks                                202425052500                       # Number of ticks simulated
final_tick                               202425052500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 117924                       # Simulator instruction rate (inst/s)
host_op_rate                                   132952                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               47246555                       # Simulator tick rate (ticks/s)
host_mem_usage                                 317744                       # Number of bytes of host memory used
host_seconds                                  4284.44                       # Real time elapsed on the host
sim_insts                                   505237723                       # Number of instructions simulated
sim_ops                                     569624283                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            216128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9265920                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9482048                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       216128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          216128                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6248320                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6248320                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3377                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144780                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                148157                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97630                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97630                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              1067694                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             45774571                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                46842265                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1067694                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1067694                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          30867326                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               30867326                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          30867326                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1067694                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            45774571                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               77709591                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        148159                       # Number of read requests accepted
system.physmem.writeReqs                        97630                       # Number of write requests accepted
system.physmem.readBursts                      148159                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97630                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9473600                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      8576                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6247040                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9482176                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6248320                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      134                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              5                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9589                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9250                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9271                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8997                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9766                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9623                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9103                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8296                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8815                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8915                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8926                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9755                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9632                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9741                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8922                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9424                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6257                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6164                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6102                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5898                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6263                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6268                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6040                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5542                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5815                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5905                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5986                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6523                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6368                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6315                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6035                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6129                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    202425037000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  148159                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97630                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    138435                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9034                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       497                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        50                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2391                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     5335                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     5757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     5818                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5824                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5835                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5828                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5866                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5860                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5849                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5863                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5973                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5919                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5829                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5845                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5807                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        65421                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      240.288837                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     153.819388                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     255.394880                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          26636     40.71%     40.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        17331     26.49%     67.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         6016      9.20%     76.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         6235      9.53%     85.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3111      4.76%     90.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1372      2.10%     92.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          907      1.39%     94.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          656      1.00%     95.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3157      4.83%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          65421                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5723                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.864057                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      376.771836                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5718     99.91%     99.91% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            4      0.07%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5723                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5723                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.055740                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.965515                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.130372                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17            3465     60.55%     60.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19            2071     36.19%     96.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21              82      1.43%     98.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23              27      0.47%     98.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25              23      0.40%     99.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27              19      0.33%     99.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29              13      0.23%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31               7      0.12%     99.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33               3      0.05%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35               3      0.05%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37               1      0.02%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43               3      0.05%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45               1      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47               2      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51               1      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61               1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-69               1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5723                       # Writes before turning the bus around for reads
system.physmem.totQLat                     1821123750                       # Total ticks spent queuing
system.physmem.totMemAccLat                4596592500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    740125000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12302.81                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31052.81                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          46.80                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          30.86                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       46.84                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       30.87                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.61                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.37                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.24                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.07                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        19.22                       # Average write queue length when enqueuing
system.physmem.readRowHits                     115945                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     64262                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   78.33                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  65.82                       # Row buffer hit rate for writes
system.physmem.avgGap                       823572.40                       # Average gap between requests
system.physmem.pageHitRate                      73.36                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     121085417750                       # Time in different power states
system.physmem.memoryStateTime::REF        6759220000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       74577349250                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     77709591                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               46864                       # Transaction distribution
system.membus.trans_dist::ReadResp              46862                       # Transaction distribution
system.membus.trans_dist::Writeback             97630                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                5                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               5                       # Transaction distribution
system.membus.trans_dist::ReadExReq            101295                       # Transaction distribution
system.membus.trans_dist::ReadExResp           101295                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       393956                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 393956                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15730368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            15730368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               15730368                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1082435500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1397409745                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               182802818                       # Number of BP lookups
system.cpu.branchPred.condPredicted         143112021                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           7267941                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             93011295                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                87213055                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             93.766090                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                12678218                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             116271                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        404850106                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          119389916                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      761628718                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   182802818                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           99891273                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     170150143                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                35691365                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               77449263                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   42                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           486                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           26                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 114538694                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2440341                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          394609388                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.164838                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.986971                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                224471880     56.88%     56.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 14182431      3.59%     60.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 22892997      5.80%     66.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 22746730      5.76%     72.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 20891038      5.29%     77.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 11596009      2.94%     80.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 13056866      3.31%     83.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 12000205      3.04%     86.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 52771232     13.37%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            394609388                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.451532                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.881261                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                129090145                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              72932890                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158811519                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               6229483                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               27545351                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             26129524                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 76858                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              825625828                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                295316                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               27545351                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                135687065                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                10105791                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       47805401                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158260364                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              15205416                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              800656323                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1334                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                3053839                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               8954907                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              385                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           954272169                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3518760229                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3237464445                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               416                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             666252291                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                288019878                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            2292922                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        2292918                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  41836509                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            170268509                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            73501316                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          28634884                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         15888043                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  755077640                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             3775313                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 665327015                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1386285                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       187386746                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    479953007                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         797681                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     394609388                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.686039                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.735073                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           139096453     35.25%     35.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            69938770     17.72%     52.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            71532009     18.13%     71.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            53395901     13.53%     84.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            31139583      7.89%     92.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15999118      4.05%     96.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             8786717      2.23%     98.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             2904396      0.74%     99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1816441      0.46%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       394609388                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  479561      5.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                6536466     68.14%     73.13% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2577260     26.87%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             447787138     67.30%     67.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               383414      0.06%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  94      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            153368040     23.05%     90.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            63788326      9.59%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              665327015                       # Type of FU issued
system.cpu.iq.rate                           1.643391                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     9593287                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014419                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1736242767                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         947046337                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    646056325                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 223                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                298                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              674920189                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     113                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          8551877                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     44238954                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        41472                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       810610                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     16640839                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        19493                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          7969                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               27545351                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 5256121                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                385567                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           760412013                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1120947                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             170268509                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             73501316                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            2286771                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 219704                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 12090                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         810610                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4341838                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4001214                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8343052                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             655907838                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             150084771                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           9419177                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1559060                       # number of nop insts executed
system.cpu.iew.exec_refs                    212583673                       # number of memory reference insts executed
system.cpu.iew.exec_branches                138498504                       # Number of branches executed
system.cpu.iew.exec_stores                   62498902                       # Number of stores executed
system.cpu.iew.exec_rate                     1.620125                       # Inst execution rate
system.cpu.iew.wb_sent                      651026464                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     646056341                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 374698942                       # num instructions producing a value
system.cpu.iew.wb_consumers                 646299992                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.595791                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.579760                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       189472037                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           7193780                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    367064037                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.555500                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.230573                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    159337830     43.41%     43.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     98602437     26.86%     70.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     33803348      9.21%     79.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     18720540      5.10%     84.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     16173781      4.41%     88.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7454535      2.03%     91.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      6985415      1.90%     92.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3172083      0.86%     93.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22814068      6.22%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    367064037                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            506581607                       # Number of instructions committed
system.cpu.commit.committedOps              570968167                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      182890032                       # Number of memory references committed
system.cpu.commit.loads                     126029555                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  121548301                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 470727693                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        387738913     67.91%     67.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          339219      0.06%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     67.97% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       126029555     22.07%     90.04% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       56860477      9.96%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         570968167                       # Class of committed instruction
system.cpu.commit.bw_lim_events              22814068                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1104683035                       # The number of ROB reads
system.cpu.rob.rob_writes                  1548546574                       # The number of ROB writes
system.cpu.timesIdled                          329089                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        10240718                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   505237723                       # Number of Instructions Simulated
system.cpu.committedOps                     569624283                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.801306                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.801306                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.247962                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.247962                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3058680468                       # number of integer regfile reads
system.cpu.int_regfile_writes               751974394                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads               237852228                       # number of misc regfile reads
system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               734945552                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq         864760                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        864758                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1110914                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           63                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           63                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       348881                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       348881                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        33826                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3504415                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3538241                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1079872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    147686464                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      148766336                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         148766336                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus         5056                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2273224996                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      26000486                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1824563475                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.icache.tags.replacements             15031                       # number of replacements
system.cpu.icache.tags.tagsinuse          1100.518238                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           114517542                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             16885                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           6782.205626                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1100.518238                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.537362                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.537362                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1854                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           55                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          292                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.905273                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         229094338                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        229094338                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    114517542                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       114517542                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     114517542                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        114517542                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    114517542                       # number of overall hits
system.cpu.icache.overall_hits::total       114517542                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        21151                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         21151                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        21151                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          21151                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        21151                       # number of overall misses
system.cpu.icache.overall_misses::total         21151                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    554005735                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    554005735                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    554005735                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    554005735                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    554005735                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    554005735                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    114538693                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    114538693                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    114538693                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    114538693                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    114538693                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    114538693                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000185                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000185                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000185                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000185                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000185                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000185                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26192.886152                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 26192.886152                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26192.886152                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 26192.886152                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26192.886152                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 26192.886152                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          775                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    51.666667                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4198                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         4198                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         4198                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         4198                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         4198                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         4198                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16953                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        16953                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        16953                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        16953                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        16953                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        16953                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    401201263                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    401201263                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    401201263                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    401201263                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    401201263                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    401201263                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000148                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000148                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000148                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000148                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23665.502448                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23665.502448                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23665.502448                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 23665.502448                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23665.502448                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23665.502448                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           115416                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27085.834103                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1781268                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           146665                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.145147                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      89916309500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23017.620858                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   361.438946                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3706.774299                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.702442                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011030                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.113122                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.826594                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31249                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           70                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2194                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7681                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21304                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.953644                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         19091917                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        19091917                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        13492                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       804297                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         817789                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1110914                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1110914                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           59                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           59                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       247585                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       247585                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        13492                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1051882                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1065374                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        13492                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1051882                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1065374                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3382                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        43510                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        46892                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            4                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            4                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       101296                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       101296                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3382                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       144806                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        148188                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3382                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       144806                       # number of overall misses
system.cpu.l2cache.overall_misses::total       148188                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    248983750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3325064500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3574048250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7369870249                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7369870249                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    248983750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10694934749                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10943918499                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    248983750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10694934749                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10943918499                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        16874                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       847807                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       864681                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1110914                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1110914                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           63                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           63                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       348881                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       348881                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        16874                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1196688                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1213562                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        16874                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1196688                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1213562                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.200427                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051321                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.054230                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.063492                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.063492                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290345                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.290345                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200427                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.121006                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.122110                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200427                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.121006                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.122110                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73620.269072                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76420.696392                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76218.720677                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72755.787484                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72755.787484                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73620.269072                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73856.986237                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73851.583792                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73620.269072                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73856.986237                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73851.583792                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97630                       # number of writebacks
system.cpu.l2cache.writebacks::total            97630                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           24                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           28                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           28                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           24                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           28                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3378                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43486                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        46864                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            4                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            4                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101296                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       101296                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3378                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       144782                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       148160                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3378                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       144782                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       148160                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    206192500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2779400500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2985593000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        40004                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        40004                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6084575751                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6084575751                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    206192500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8863976251                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9070168751                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    206192500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8863976251                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9070168751                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.200190                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051292                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054198                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.063492                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.063492                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290345                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290345                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200190                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.120986                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.122087                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200190                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.120986                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.122087                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61039.816459                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63914.834659                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.600717                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60067.285490                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60067.285490                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61039.816459                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61222.916184                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61218.741570                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61039.816459                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61222.916184                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61218.741570                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1192591                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4057.481628                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           190175522                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1196687                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            158.918349                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4252802250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4057.481628                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.990596                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.990596                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2354                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         1688                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         391451119                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        391451119                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    136209146                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       136209146                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     50988846                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       50988846                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488796                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488796                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     187197992                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        187197992                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    187197992                       # number of overall hits
system.cpu.dcache.overall_hits::total       187197992                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1701390                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1701390                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3250460                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3250460                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           37                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           37                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4951850                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4951850                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4951850                       # number of overall misses
system.cpu.dcache.overall_misses::total       4951850                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  29115477457                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  29115477457                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  71211038449                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  71211038449                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       609500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       609500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 100326515906                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 100326515906                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 100326515906                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 100326515906                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    137910536                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    137910536                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488833                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488833                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    192149842                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    192149842                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    192149842                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    192149842                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012337                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.012337                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059928                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.059928                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000025                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000025                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025771                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025771                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025771                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025771                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17112.759248                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17112.759248                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21907.987931                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 21907.987931                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16472.972973                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16472.972973                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20260.410939                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20260.410939                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20260.410939                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20260.410939                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        17276                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        49920                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1691                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             664                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.216440                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    75.180723                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1110914                       # number of writebacks
system.cpu.dcache.writebacks::total           1110914                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       853047                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       853047                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2902052                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2902052                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           37                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           37                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3755099                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3755099                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3755099                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3755099                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848343                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       848343                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348408                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       348408                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1196751                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1196751                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1196751                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1196751                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12254549779                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12254549779                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10243730741                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10243730741                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22498280520                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  22498280520                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22498280520                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  22498280520                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006151                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006151                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006424                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006424                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006228                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006228                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14445.277180                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14445.277180                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29401.537109                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29401.537109                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18799.466656                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18799.466656                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18799.466656                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18799.466656                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------