path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.202697                       # Number of seconds simulated
sim_ticks                                202696649500                       # Number of ticks simulated
final_tick                               202696649500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 142513                       # Simulator instruction rate (inst/s)
host_op_rate                                   160675                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               57175030                       # Simulator tick rate (ticks/s)
host_mem_usage                                 274024                       # Number of bytes of host memory used
host_seconds                                  3545.20                       # Real time elapsed on the host
sim_insts                                   505237723                       # Number of instructions simulated
sim_ops                                     569624283                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            215936                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9269696                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9485632                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       215936                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          215936                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6249792                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6249792                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3374                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144839                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                148213                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97653                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97653                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              1065316                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             45731866                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                46797182                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1065316                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1065316                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          30833228                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               30833228                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          30833228                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1065316                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            45731866                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               77630410                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        148213                       # Number of read requests accepted
system.physmem.writeReqs                        97653                       # Number of write requests accepted
system.physmem.readBursts                      148213                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97653                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9481152                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      4480                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6249152                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9485632                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6249792                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       70                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              7                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9594                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9237                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9258                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8983                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9776                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9641                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9120                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8318                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8799                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8914                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8952                       # Per bank write bursts
system.physmem.perBankRdBursts::11               9727                       # Per bank write bursts
system.physmem.perBankRdBursts::12               9657                       # Per bank write bursts
system.physmem.perBankRdBursts::13               9778                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8939                       # Per bank write bursts
system.physmem.perBankRdBursts::15               9450                       # Per bank write bursts
system.physmem.perBankWrBursts::0                6271                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6158                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6091                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5883                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6254                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6272                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6041                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5553                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5808                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5908                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5990                       # Per bank write bursts
system.physmem.perBankWrBursts::11               6516                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6373                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6333                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6051                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6141                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    202696525000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  148213                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97653                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    138426                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9137                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       517                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        50                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4462                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4491                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4457                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4477                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4461                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4448                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4427                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4427                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4424                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4429                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4442                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4421                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4459                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4501                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        1                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        69151                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      227.469277                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     137.950297                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     327.311281                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64             32073     46.38%     46.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128            12750     18.44%     64.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192             5391      7.80%     72.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256             3340      4.83%     77.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320             2388      3.45%     80.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384             2364      3.42%     84.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448             3443      4.98%     89.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512             1961      2.84%     92.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576              807      1.17%     93.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640              577      0.83%     94.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704              471      0.68%     94.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768              358      0.52%     95.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832              272      0.39%     95.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896              260      0.38%     96.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960              188      0.27%     96.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024             160      0.23%     96.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088             170      0.25%     96.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152             142      0.21%     97.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216             124      0.18%     97.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280             152      0.22%     97.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344             134      0.19%     97.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408             815      1.18%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472             105      0.15%     98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536             136      0.20%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600              73      0.11%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664              89      0.13%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728              48      0.07%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792              64      0.09%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856              20      0.03%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920              34      0.05%     99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984              22      0.03%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048              21      0.03%     99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112               9      0.01%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176              15      0.02%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240               7      0.01%     99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304              10      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368               5      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432               4      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496               7      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560               7      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624              10      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688               8      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752               7      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816               6      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880               4      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944               4      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008               2      0.00%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072               4      0.01%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136               2      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200               3      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264               4      0.01%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328               5      0.01%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392               2      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456               1      0.00%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520               4      0.01%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584               4      0.01%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648               3      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712               2      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776               4      0.01%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904               1      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968               1      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032               2      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096               2      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160               1      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224               2      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352               1      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416               4      0.01%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480               1      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544               3      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608               1      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672               3      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736               1      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800               4      0.01%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864               4      0.01%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928               6      0.01%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992               8      0.01%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056               4      0.01%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120               4      0.01%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          69151                       # Bytes accessed per row activation
system.physmem.totQLat                     1733842500                       # Total ticks spent queuing
system.physmem.totMemAccLat                4938805000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    740715000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  2464247500                       # Total ticks spent accessing banks
system.physmem.avgQLat                       11703.84                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    16634.25                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  33338.09                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          46.78                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          30.83                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       46.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       30.83                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.61                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.37                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.24                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         8.92                       # Average write queue length when enqueuing
system.physmem.readRowHits                     118670                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     57965                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.11                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  59.36                       # Row buffer hit rate for writes
system.physmem.avgGap                       824418.69                       # Average gap between requests
system.physmem.pageHitRate                      71.86                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               4.58                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     77630410                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               46935                       # Transaction distribution
system.membus.trans_dist::ReadResp              46935                       # Transaction distribution
system.membus.trans_dist::Writeback             97653                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                7                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               7                       # Transaction distribution
system.membus.trans_dist::ReadExReq            101278                       # Transaction distribution
system.membus.trans_dist::ReadExResp           101278                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       394093                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 394093                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15735424                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            15735424                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               15735424                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1083458000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1398218993                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               182767812                       # Number of BP lookups
system.cpu.branchPred.condPredicted         143090812                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           7262422                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             93142512                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                87193307                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             93.612793                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                12680291                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             116092                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        405393300                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          119358761                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      761461935                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   182767812                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           99873598                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     170116443                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                35667741                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               77537943                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   37                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           427                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           15                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 114511433                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2436940                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          394614975                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.164245                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.986660                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                224511182     56.89%     56.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 14185619      3.59%     60.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 22882928      5.80%     66.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 22735959      5.76%     72.05% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 20902964      5.30%     77.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 11599090      2.94%     80.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 13052635      3.31%     83.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 11995684      3.04%     86.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 52748914     13.37%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            394614975                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.450841                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.878329                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                129045860                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              73029235                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 158776788                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               6235766                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               27527326                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             26113836                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 76704                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              825433505                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                295928                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               27527326                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                135634392                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                10115343                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       47882338                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158241210                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              15214366                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              800503248                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1357                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                3055222                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               8963577                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              323                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           954180101                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3518022066                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3236814887                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               408                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             666252291                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                287927810                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            2293035                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        2293033                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  41823481                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            170244853                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            73468690                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          28584671                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         15947575                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  754970143                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             3775446                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 665247715                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1368678                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       187299729                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    479807189                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         797814                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     394614975                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.685815                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.734907                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           139112608     35.25%     35.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            69963718     17.73%     52.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            71480339     18.11%     71.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            53412881     13.54%     84.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            31169155      7.90%     92.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15993671      4.05%     96.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             8759011      2.22%     98.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             2903101      0.74%     99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1820491      0.46%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       394614975                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  480625      5.03%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      5.03% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                6529255     68.28%     73.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2553152     26.70%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             447743251     67.30%     67.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               383309      0.06%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  94      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.36% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            153363071     23.05%     90.42% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            63757987      9.58%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              665247715                       # Type of FU issued
system.cpu.iq.rate                           1.640993                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     9563032                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014375                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1736041890                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         946851577                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    645982069                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 225                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                304                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              674810634                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     113                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          8546846                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     44215298                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        41270                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       810207                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     16608213                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        19520                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          8279                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               27527326                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 5271033                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                384981                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           760303523                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1119045                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             170244853                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             73468690                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            2286904                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 219731                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11453                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         810207                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4335544                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4001823                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8337367                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             655831134                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             150081839                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           9416581                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1557934                       # number of nop insts executed
system.cpu.iew.exec_refs                    212547196                       # number of memory reference insts executed
system.cpu.iew.exec_branches                138487054                       # Number of branches executed
system.cpu.iew.exec_stores                   62465357                       # Number of stores executed
system.cpu.iew.exec_rate                     1.617765                       # Inst execution rate
system.cpu.iew.wb_sent                      650951989                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     645982085                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 374676308                       # num instructions producing a value
system.cpu.iew.wb_consumers                 646230138                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.593470                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.579788                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       189364408                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           7188399                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    367087649                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.555400                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.230509                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    159393543     43.42%     43.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     98511772     26.84%     70.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     33830447      9.22%     79.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     18783252      5.12%     84.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     16176645      4.41%     89.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7442765      2.03%     91.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      6952611      1.89%     92.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3163238      0.86%     93.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22833376      6.22%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    367087649                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            506581607                       # Number of instructions committed
system.cpu.commit.committedOps              570968167                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      182890032                       # Number of memory references committed
system.cpu.commit.loads                     126029555                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  121548301                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 470727693                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              22833376                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1104579710                       # The number of ROB reads
system.cpu.rob.rob_writes                  1548313166                       # The number of ROB writes
system.cpu.timesIdled                          328667                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        10778325                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   505237723                       # Number of Instructions Simulated
system.cpu.committedOps                     569624283                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             505237723                       # Number of Instructions Simulated
system.cpu.cpi                               0.802381                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.802381                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.246290                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.246290                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3058357965                       # number of integer regfile reads
system.cpu.int_regfile_writes               751931601                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads               237823379                       # number of misc regfile reads
system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               733902057                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq         864632                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        864632                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1110906                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           71                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           71                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       348829                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       348829                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        33629                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3504262                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3537891                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1073600                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    147680832                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      148754432                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         148754432                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus         5056                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     2273126497                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      25848480                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1823961981                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.icache.tags.replacements             14927                       # number of replacements
system.cpu.icache.tags.tagsinuse          1097.546967                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           114490465                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             16785                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           6820.998808                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1097.546967                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.535912                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.535912                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1858                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           78                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          302                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1380                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.907227                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         229039718                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        229039718                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    114490465                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       114490465                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     114490465                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        114490465                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    114490465                       # number of overall hits
system.cpu.icache.overall_hits::total       114490465                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        20967                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         20967                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        20967                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          20967                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        20967                       # number of overall misses
system.cpu.icache.overall_misses::total         20967                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    566965977                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    566965977                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    566965977                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    566965977                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    566965977                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    566965977                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    114511432                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    114511432                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    114511432                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    114511432                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    114511432                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    114511432                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000183                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000183                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000183                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000183                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000183                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000183                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27040.872657                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 27040.872657                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27040.872657                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 27040.872657                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27040.872657                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 27040.872657                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1029                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    85.750000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4113                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         4113                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         4113                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         4113                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         4113                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         4113                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16854                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        16854                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        16854                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        16854                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        16854                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        16854                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    413760769                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    413760769                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    413760769                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    413760769                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    413760769                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    413760769                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000147                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000147                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000147                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000147                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000147                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000147                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24549.707429                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24549.707429                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24549.707429                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 24549.707429                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24549.707429                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 24549.707429                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           115464                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        27088.798678                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1780777                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           146712                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.137910                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     102535173000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23012.092696                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   360.882153                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  3715.823828                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.702273                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.011013                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.113398                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.826685                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31248                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2200                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7669                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        21308                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.953613                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         19090479                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        19090479                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        13395                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       804194                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         817589                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1110906                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1110906                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           66                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           66                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       247549                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       247549                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        13395                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1051743                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1065138                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        13395                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1051743                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1065138                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3380                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        43584                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        46964                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       101280                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       101280                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3380                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       144864                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        148244                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3380                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       144864                       # number of overall misses
system.cpu.l2cache.overall_misses::total       148244                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    262616000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   3492071500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3754687500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7549884498                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   7549884498                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    262616000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  11041955998                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  11304571998                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    262616000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  11041955998                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  11304571998                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        16775                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       847778                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       864553                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1110906                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1110906                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           71                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           71                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       348829                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       348829                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        16775                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1196607                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1213382                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        16775                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1196607                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1213382                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.201490                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051410                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.054322                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.070423                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.070423                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290343                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.290343                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.201490                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.121062                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.122174                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.201490                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.121062                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.122174                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77697.041420                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80122.785885                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79948.205008                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74544.673164                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74544.673164                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77697.041420                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76222.912511                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76256.523016                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77697.041420                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76222.912511                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76256.523016                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97653                       # number of writebacks
system.cpu.l2cache.writebacks::total            97653                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           23                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           29                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            6                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           23                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           29                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            6                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           23                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           29                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3374                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43561                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        46935                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101280                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       101280                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3374                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       144841                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       148215                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3374                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       144841                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       148215                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    219732000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2944554000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3164286000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        50005                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        50005                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6265225502                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6265225502                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    219732000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9209779502                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9429511502                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    219732000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9209779502                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9429511502                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.201133                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051383                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054288                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.070423                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.070423                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290343                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290343                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.201133                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.121043                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.122150                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.201133                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.121043                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.122150                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65125.074096                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67596.106609                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67418.472355                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61860.441370                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61860.441370                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65125.074096                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63585.445433                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63620.493891                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65125.074096                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63585.445433                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63620.493891                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1192511                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4057.506365                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           190177939                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1196607                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            158.930993                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        4256684250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4057.506365                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.990602                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.990602                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           36                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2352                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         1686                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         391455847                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        391455847                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    136212044                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       136212044                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     50988351                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       50988351                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488804                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488804                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     187200395                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        187200395                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    187200395                       # number of overall hits
system.cpu.dcache.overall_hits::total       187200395                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1700889                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1700889                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3250955                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3250955                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           36                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           36                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4951844                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4951844                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4951844                       # number of overall misses
system.cpu.dcache.overall_misses::total       4951844                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  29691567711                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  29691567711                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  72513714730                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  72513714730                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       595500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       595500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 102205282441                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 102205282441                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 102205282441                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 102205282441                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    137912933                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    137912933                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488840                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488840                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    192152239                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    192152239                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    192152239                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    192152239                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012333                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.012333                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059937                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.059937                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000024                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000024                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025770                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025770                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025770                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025770                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17456.499343                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17456.499343                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22305.357881                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 22305.357881                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16541.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16541.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20639.842944                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20639.842944                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20639.842944                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 20639.842944                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        17574                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        52604                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1663                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             661                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.567649                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    79.582451                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1110906                       # number of writebacks
system.cpu.dcache.writebacks::total           1110906                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       852565                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       852565                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2902601                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2902601                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           36                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           36                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3755166                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3755166                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3755166                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3755166                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848324                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       848324                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348354                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       348354                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1196678                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1196678                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1196678                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1196678                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12420423026                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  12420423026                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10423297989                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  10423297989                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22843721015                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  22843721015                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22843721015                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  22843721015                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006151                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006151                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006423                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006423                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006228                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006228                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006228                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14641.131249                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14641.131249                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29921.568258                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29921.568258                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.279668                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.279668                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.279668                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.279668                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------