path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.234067                       # Number of seconds simulated
sim_ticks                                234067145000                       # Number of ticks simulated
final_tick                               234067145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  77703                       # Simulator instruction rate (inst/s)
host_op_rate                                    84180                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               35998538                       # Simulator tick rate (ticks/s)
host_mem_usage                                 329176                       # Number of bytes of host memory used
host_seconds                                  6502.13                       # Real time elapsed on the host
sim_insts                                   505234934                       # Number of instructions simulated
sim_ops                                     547348155                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            528384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10113344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     16488320                       # Number of bytes read from this memory
system.physmem.bytes_read::total             27130048                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       528384                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          528384                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18753344                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18753344                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               8256                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             158021                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       257630                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                423907                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          293021                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               293021                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              2257404                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             43207021                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     70442693                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               115907117                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2257404                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2257404                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          80119506                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               80119506                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          80119506                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2257404                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            43207021                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     70442693                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              196026623                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        423907                       # Number of read requests accepted
system.physmem.writeReqs                       293021                       # Number of write requests accepted
system.physmem.readBursts                      423907                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     293021                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 26979584                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                    150464                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18751744                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  27130048                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18753344                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                     2351                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       6                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               26590                       # Per bank write bursts
system.physmem.perBankRdBursts::1               25594                       # Per bank write bursts
system.physmem.perBankRdBursts::2               25276                       # Per bank write bursts
system.physmem.perBankRdBursts::3               32211                       # Per bank write bursts
system.physmem.perBankRdBursts::4               27176                       # Per bank write bursts
system.physmem.perBankRdBursts::5               28517                       # Per bank write bursts
system.physmem.perBankRdBursts::6               25342                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24044                       # Per bank write bursts
system.physmem.perBankRdBursts::8               25598                       # Per bank write bursts
system.physmem.perBankRdBursts::9               25550                       # Per bank write bursts
system.physmem.perBankRdBursts::10              25481                       # Per bank write bursts
system.physmem.perBankRdBursts::11              26074                       # Per bank write bursts
system.physmem.perBankRdBursts::12              27377                       # Per bank write bursts
system.physmem.perBankRdBursts::13              26182                       # Per bank write bursts
system.physmem.perBankRdBursts::14              25062                       # Per bank write bursts
system.physmem.perBankRdBursts::15              25482                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18771                       # Per bank write bursts
system.physmem.perBankWrBursts::1               18326                       # Per bank write bursts
system.physmem.perBankWrBursts::2               17966                       # Per bank write bursts
system.physmem.perBankWrBursts::3               17954                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18603                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18522                       # Per bank write bursts
system.physmem.perBankWrBursts::6               18156                       # Per bank write bursts
system.physmem.perBankWrBursts::7               17645                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18039                       # Per bank write bursts
system.physmem.perBankWrBursts::9               17820                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18389                       # Per bank write bursts
system.physmem.perBankWrBursts::11              18735                       # Per bank write bursts
system.physmem.perBankWrBursts::12              18802                       # Per bank write bursts
system.physmem.perBankWrBursts::13              18436                       # Per bank write bursts
system.physmem.perBankWrBursts::14              18499                       # Per bank write bursts
system.physmem.perBankWrBursts::15              18333                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    234067092500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  423907                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 293021                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    324297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     49438                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     12772                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      8887                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      7182                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      6051                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      5178                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4282                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3308                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        79                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       41                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       22                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     7217                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     7709                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    12444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    14936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    16344                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    16981                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17377                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17969                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    18131                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    18327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    18655                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    18757                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    18967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    19091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17198                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       323145                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      141.515567                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      99.534760                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     179.780407                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         203801     63.07%     63.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        79524     24.61%     87.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        15124      4.68%     92.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7403      2.29%     94.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         4958      1.53%     96.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2458      0.76%     96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1821      0.56%     97.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1542      0.48%     97.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         6514      2.02%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         323145                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17117                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.623824                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      142.773249                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          17115     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::18432-19455            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17117                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17117                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.117252                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.059352                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.476775                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               9319     54.44%     54.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                336      1.96%     56.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               5339     31.19%     87.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19               1368      7.99%     95.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                375      2.19%     97.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                151      0.88%     98.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 90      0.53%     99.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 54      0.32%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 43      0.25%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 14      0.08%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 11      0.06%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  3      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  5      0.03%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  2      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38                  2      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17117                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8655442270                       # Total ticks spent queuing
system.physmem.totMemAccLat               16559617270                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2107780000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       20532.13                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  39282.13                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         115.26                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          80.11                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      115.91                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       80.12                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.53                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.90                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.63                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.74                       # Average write queue length when enqueuing
system.physmem.readRowHits                     306165                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     85234                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   72.63                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  29.09                       # Row buffer hit rate for writes
system.physmem.avgGap                       326486.19                       # Average gap between requests
system.physmem.pageHitRate                      54.77                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1230881400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  671611875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1674738000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                945710640                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            15287822160                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            82093251645                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            68426008500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             170330024220                       # Total energy per rank (pJ)
system.physmem_0.averagePower              727.711031                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   113299566780                       # Time in different power states
system.physmem_0.memoryStateTime::REF      7815860000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    112947723720                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1211996520                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  661307625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1612860600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                952903440                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            15287822160                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            79567358490                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            70641696000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             169935944835                       # Total energy per rank (pJ)
system.physmem_1.averagePower              726.027425                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   117000888833                       # Time in different power states
system.physmem_1.memoryStateTime::REF      7815860000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    109246895167                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               175180766                       # Number of BP lookups
system.cpu.branchPred.condPredicted         131398582                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           7457767                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             90448674                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                83962981                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             92.829422                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                12120591                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             103810                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        468134291                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            7820267                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      732116673                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   175180766                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           96083572                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     452171073                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                14968467                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 4602                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            73                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        11985                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 236801931                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 34000                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          467492233                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.696108                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.181518                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 95390302     20.40%     20.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                132755119     28.40%     48.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 57878050     12.38%     61.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                181468762     38.82%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            467492233                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.374210                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.563903                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 32386715                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             118994468                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 287021244                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              22094342                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                6995464                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             24069927                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                496423                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              716090334                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              30070891                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                6995464                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 63523233                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                55798726                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       40379426                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 276600311                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              24195073                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              686795271                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              13387267                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               9456751                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2380300                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                1659301                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1902126                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           831315383                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3020004146                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        724106734                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               424                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             654095674                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                177219709                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            1544715                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        1534907                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  42449008                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            143548530                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            67987102                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          12901487                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         11312004                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  668319179                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             2978345                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 610345579                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           5883396                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       123949369                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    319552681                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            713                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     467492233                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.305574                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.102144                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           150289114     32.15%     32.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           101200175     21.65%     53.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           145769872     31.18%     84.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            63327215     13.55%     98.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6905270      1.48%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 587      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       467492233                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                71934630     52.97%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     30      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.97% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               44579938     32.83%     85.80% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              19275701     14.20%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             413246027     67.71%     67.71% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               352054      0.06%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            134225887     21.99%     89.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            62521608     10.24%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              610345579                       # Type of FU issued
system.cpu.iq.rate                           1.303783                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   135790299                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.222481                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1829856789                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         795275233                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    595043365                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 297                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                322                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              746135699                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     179                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          7278929                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     27665247                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        25667                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        29087                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     11126882                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       224857                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         22662                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                6995464                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                22964751                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                919913                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           672785382                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             143548530                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             67987102                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            1489803                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 257985                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                525401                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          29087                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3817186                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3742282                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              7559468                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             599464871                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             129581939                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10880708                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1487858                       # number of nop insts executed
system.cpu.iew.exec_refs                    190527023                       # number of memory reference insts executed
system.cpu.iew.exec_branches                131393815                       # Number of branches executed
system.cpu.iew.exec_stores                   60945084                       # Number of stores executed
system.cpu.iew.exec_rate                     1.280540                       # Inst execution rate
system.cpu.iew.wb_sent                      596341042                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     595043381                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 349946127                       # num instructions producing a value
system.cpu.iew.wb_consumers                 570674546                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.271095                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.613215                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts       110160125                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           6968998                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    450355888                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.218352                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.886219                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    221337598     49.15%     49.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    116324478     25.83%     74.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     43749692      9.71%     84.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     23265748      5.17%     89.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     11567595      2.57%     92.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7783316      1.73%     94.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      8242109      1.83%     95.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      4251497      0.94%     96.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     13833855      3.07%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    450355888                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            506578818                       # Number of instructions committed
system.cpu.commit.committedOps              548692039                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      172743503                       # Number of memory references committed
system.cpu.commit.loads                     115883283                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  121552863                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 448447003                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        375609314     68.46%     68.46% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          339219      0.06%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            3      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     68.52% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       115883283     21.12%     89.64% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       56860220     10.36%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         548692039                       # Class of committed instruction
system.cpu.commit.bw_lim_events              13833855                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1095367059                       # The number of ROB reads
system.cpu.rob.rob_writes                  1334871218                       # The number of ROB writes
system.cpu.timesIdled                           12751                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          642058                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   505234934                       # Number of Instructions Simulated
system.cpu.committedOps                     547348155                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.926568                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.926568                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.079252                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.079252                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                611137722                       # number of integer regfile reads
system.cpu.int_regfile_writes               328167949                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.cc_regfile_reads                2170388141                       # number of cc regfile reads
system.cpu.cc_regfile_writes                376631000                       # number of cc regfile writes
system.cpu.misc_regfile_reads               217967292                       # number of misc regfile reads
system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2817526                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.629948                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           169361200                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2818038                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             60.098977                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         500883000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.629948                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999277                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999277                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         356245262                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        356245262                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    114657971                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       114657971                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     51723280                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       51723280                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         2781                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          2781                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488558                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      1488558                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     166381251                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        166381251                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    166384032                       # number of overall hits
system.cpu.dcache.overall_hits::total       166384032                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      4836633                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       4836633                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2515769                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2515769                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           67                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           67                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      7352402                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        7352402                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      7352414                       # number of overall misses
system.cpu.dcache.overall_misses::total       7352414                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  57448748500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  57448748500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  18924298425                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  18924298425                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       887000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       887000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  76373046925                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  76373046925                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  76373046925                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  76373046925                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    119494604                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    119494604                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         2793                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         2793                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488625                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      1488625                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    173733653                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    173733653                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    173736446                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    173736446                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040476                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.040476                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046383                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.046383                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004296                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.004296                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000045                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000045                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.042320                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.042320                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.042319                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.042319                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11877.839088                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11877.839088                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7522.271888                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  7522.271888                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13238.805970                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13238.805970                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10387.496076                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10387.496076                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10387.479123                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10387.479123                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           15                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       910856                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          221280                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           15                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     4.116305                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2817526                       # number of writebacks
system.cpu.dcache.writebacks::total           2817526                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2538406                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      2538406                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1995936                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1995936                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           67                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           67                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      4534342                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      4534342                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      4534342                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      4534342                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2298227                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      2298227                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519833                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       519833                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2818060                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2818060                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2818070                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2818070                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29530364500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  29530364500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4603208492                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4603208492                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       671000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       671000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  34133572992                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  34133572992                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  34134243992                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  34134243992                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019233                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019233                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009584                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009584                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003580                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003580                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016221                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.016221                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016220                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.016220                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12849.193966                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12849.193966                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8855.167894                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8855.167894                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        67100                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        67100                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.436567                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.436567                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.631692                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.631692                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             73421                       # number of replacements
system.cpu.icache.tags.tagsinuse           466.150305                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           236720018                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             73932                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           3201.861413                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      115595672500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   466.150305                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.910450                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.910450                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          258                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          120                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           17                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         473677631                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        473677631                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    236720018                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       236720018                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     236720018                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        236720018                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    236720018                       # number of overall hits
system.cpu.icache.overall_hits::total       236720018                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        81816                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         81816                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        81816                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          81816                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        81816                       # number of overall misses
system.cpu.icache.overall_misses::total         81816                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1337252702                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1337252702                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1337252702                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1337252702                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1337252702                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1337252702                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    236801834                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    236801834                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    236801834                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    236801834                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    236801834                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    236801834                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000346                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000346                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000346                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000346                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000346                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000346                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16344.635548                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16344.635548                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16344.635548                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16344.635548                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16344.635548                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16344.635548                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       158150                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          252                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              6634                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    23.839313                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    50.400000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        73421                       # number of writebacks
system.cpu.icache.writebacks::total             73421                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7851                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         7851                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         7851                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         7851                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         7851                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         7851                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        73965                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        73965                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        73965                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        73965                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        73965                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        73965                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1106045298                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1106045298                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1106045298                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1106045298                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1106045298                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1106045298                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000312                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000312                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000312                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000312                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000312                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000312                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14953.630744                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14953.630744                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14953.630744                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14953.630744                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14953.630744                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14953.630744                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued      8512826                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      8514409                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit          561                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage       743711                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           395988                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        15132.629454                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3179530                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           411918                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             7.718842                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     170668253000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 13783.431676                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1349.197778                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.841274                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.082348                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.923622                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022         1007                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        14923                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           36                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3          235                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4          736                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          154                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4874                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6268                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3420                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.061462                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.910828                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         94799517                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        94799517                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      2352015                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      2352015                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks       515062                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total       515062                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       517153                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       517153                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        65667                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        65667                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2137304                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      2137304                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        65667                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2654457                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2720124                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        65667                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2654457                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2720124                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           32                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           32                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         5060                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         5060                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         8262                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         8262                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       158521                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       158521                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         8262                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       163581                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        171843                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         8262                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       163581                       # number of overall misses
system.cpu.l2cache.overall_misses::total       171843                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       104000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total       104000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    481607500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    481607500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    598906500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    598906500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  12080001500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  12080001500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    598906500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  12561609000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  13160515500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    598906500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  12561609000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  13160515500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      2352015                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      2352015                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks       515062                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total       515062                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           32                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           32                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       522213                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       522213                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        73929                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        73929                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2295825                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      2295825                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        73929                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2818038                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2891967                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        73929                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2818038                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2891967                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009690                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.009690                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.111756                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.111756                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.069048                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.069048                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111756                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.058048                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.059421                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111756                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.058048                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.059421                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         3250                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total         3250                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95179.347826                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95179.347826                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72489.288308                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72489.288308                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76204.424020                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76204.424020                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72489.288308                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76791.369413                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76584.530647                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72489.288308                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76791.369413                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76584.530647                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       293021                       # number of writebacks
system.cpu.l2cache.writebacks::total           293021                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1390                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         1390                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4166                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4166                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         5556                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         5561                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         5556                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         5561                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       350786                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       350786                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           32                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           32                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3670                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         3670                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         8257                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         8257                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       154355                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       154355                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         8257                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       158025                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       166282                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         8257                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       158025                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       350786                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       517068                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18631455358                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18631455358                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       467000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       467000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    333539000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    333539000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    549061000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    549061000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  10851655500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  10851655500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    549061000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11185194500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  11734255500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    549061000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11185194500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18631455358                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  30365710858                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007028                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007028                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.111688                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.111688                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.067233                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.067233                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.111688                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056076                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.057498                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.111688                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056076                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.178795                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53113.451956                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14593.750000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14593.750000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90882.561308                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90882.561308                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66496.427274                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66496.427274                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70303.232807                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70303.232807                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66496.427274                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70781.170701                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70568.404878                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66496.427274                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70781.170701                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58726.726191                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5782982                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2890992                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23909                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops       260193                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops       244256                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        15937                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp       2369788                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      2645036                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean       538932                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       265577                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       391986                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           32                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           32                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       522213                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       522213                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        73965                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      2295825                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       221313                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8453667                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8674980                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9430272                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    360676160                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          370106432                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      950621                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3842619                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.078093                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.283354                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            3558474     92.61%     92.61% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             268208      6.98%     99.59% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2              15937      0.41%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3842619                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5782438005                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy         1506                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     111022344                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    4227098948                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             420240                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       293021                       # Transaction distribution
system.membus.trans_dist::CleanEvict            98541                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               36                       # Transaction distribution
system.membus.trans_dist::ReadExReq              3666                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3666                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        420241                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1239411                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1239411                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45883328                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                45883328                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            815505                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  815505    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              815505                       # Request fanout histogram
system.membus.reqLayer0.occupancy          2215026289                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2242814920                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------