path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.206020                       # Number of seconds simulated
sim_ticks                                206019870500                       # Number of ticks simulated
final_tick                               206019870500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 121571                       # Simulator instruction rate (inst/s)
host_op_rate                                   136951                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               49210675                       # Simulator tick rate (ticks/s)
host_mem_usage                                 259828                       # Number of bytes of host memory used
host_seconds                                  4186.49                       # Real time elapsed on the host
sim_insts                                   508955243                       # Number of instructions simulated
sim_ops                                     573341803                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            217536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9265600                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9483136                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       217536                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          217536                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6247936                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6247936                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3399                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144775                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                148174                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97624                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97624                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              1055898                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             44974303                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                46030201                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1055898                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1055898                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          30326861                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               30326861                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          30326861                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1055898                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            44974303                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               76357062                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        148175                       # Total number of read requests seen
system.physmem.writeReqs                        97624                       # Total number of write requests seen
system.physmem.cpureqs                         245816                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                      9483136                       # Total number of bytes read from memory
system.physmem.bytesWritten                   6247936                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                9483136                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6247936                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       95                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                 17                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  9231                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  9188                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  9343                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  8790                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  9223                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  8971                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  9240                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  9470                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  9143                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 10294                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 9679                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 9702                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 9116                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 8946                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 9014                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 8730                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  5976                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  6116                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  6116                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  5942                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  6120                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  5953                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  6022                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  6372                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  5971                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  6671                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 6280                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 6315                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 6042                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 6059                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 5905                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 5764                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    206019849500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  148175                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  97624                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                   17                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    138261                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9196                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       546                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4242                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4244                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     1627412180                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                4699930180                       # Sum of mem lat for all requests
system.physmem.totBusLat                    592320000                       # Total cycles spent in databus access
system.physmem.totBankLat                  2480198000                       # Total cycles spent in bank access
system.physmem.avgQLat                       10990.09                       # Average queueing delay per request
system.physmem.avgBankLat                    16749.04                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  31739.13                       # Average memory access latency
system.physmem.avgRdBW                          46.03                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          30.33                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  46.03                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                  30.33                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.48                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.02                       # Average read queue length over time
system.physmem.avgWrQLen                         8.48                       # Average write queue length over time
system.physmem.readRowHits                     128585                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     35174                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   86.83                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  36.03                       # Row buffer hit rate for writes
system.physmem.avgGap                       838163.90                       # Average gap between requests
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        412039742                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                182071983                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          142381295                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            7268299                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              93564777                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 88700041                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                 12685099                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              116083                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          117148048                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      763048101                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   182071983                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          101385140                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     170894035                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                35686363                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               89221488                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   22                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           506                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           45                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 113043343                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2441081                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          404881843                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.113466                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.961359                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                234000478     57.79%     57.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 14180958      3.50%     61.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 22900692      5.66%     66.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 22746852      5.62%     72.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 20902415      5.16%     77.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 13082439      3.23%     80.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 13044714      3.22%     84.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 11995563      2.96%     87.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 52027732     12.85%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            404881843                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.441880                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.851880                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                127553544                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              83254868                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 161072807                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               5457053                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               27543571                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             26128616                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 76844                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              833018746                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                296404                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               27543571                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                135629156                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 9608106                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       57992007                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158279608                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              15829395                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              804332023                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1038                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                3062506                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               8833795                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              346                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           960234545                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3519895125                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3519893415                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              1710                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             672200323                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                288034222                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            3037420                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        3037417                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  49050394                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            170961338                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            74175754                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          28008123                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         15620624                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  757949088                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             4467543                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 668974363                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1389643                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       187239707                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    479750925                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         746407                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     404881843                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.652271                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.728361                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           145293299     35.89%     35.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            75809300     18.72%     54.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            69100310     17.07%     71.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            53699574     13.26%     84.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            30880132      7.63%     92.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            16168967      3.99%     96.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             9289317      2.29%     98.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             3363096      0.83%     99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1277848      0.32%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       404881843                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  478346      4.98%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.98% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                6550639     68.20%     73.18% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2576691     26.82%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             449945039     67.26%     67.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               383598      0.06%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 120      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            154114870     23.04%     90.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            64530733      9.65%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              668974363                       # Type of FU issued
system.cpu.iq.rate                           1.623568                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     9605676                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014359                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1753825613                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         950462588                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    649623996                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 275                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                376                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              678579900                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     139                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          8555633                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     44188279                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        40573                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       810259                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     16571773                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        19511                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          4184                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               27543571                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 4982601                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                373964                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           763975241                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1120254                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             170961338                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             74175754                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            2978807                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 219858                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11158                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         810259                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4340256                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4003229                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8343485                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             659478369                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             150829210                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           9495994                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1558610                       # number of nop insts executed
system.cpu.iew.exec_refs                    214064543                       # number of memory reference insts executed
system.cpu.iew.exec_branches                139194602                       # Number of branches executed
system.cpu.iew.exec_stores                   63235333                       # Number of stores executed
system.cpu.iew.exec_rate                     1.600521                       # Inst execution rate
system.cpu.iew.wb_sent                      654596597                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     649624012                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 375406719                       # num instructions producing a value
system.cpu.iew.wb_consumers                 646267574                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.576605                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.580884                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       189315872                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         3721136                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           7194171                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    377338273                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.522999                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.206666                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    165593996     43.88%     43.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    102356552     27.13%     71.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     34023160      9.02%     80.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     18860248      5.00%     85.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     16133947      4.28%     89.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7612237      2.02%     91.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      6942439      1.84%     93.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3075088      0.81%     93.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22740606      6.03%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    377338273                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            510299127                       # Number of instructions committed
system.cpu.commit.committedOps              574685687                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      184377040                       # Number of memory references committed
system.cpu.commit.loads                     126773059                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  122291805                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 473701709                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              22740606                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1118592088                       # The number of ROB reads
system.cpu.rob.rob_writes                  1555667472                       # The number of ROB writes
system.cpu.timesIdled                          306583                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         7157899                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   508955243                       # Number of Instructions Simulated
system.cpu.committedOps                     573341803                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             508955243                       # Number of Instructions Simulated
system.cpu.cpi                               0.809580                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.809580                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.235209                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.235209                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3078155858                       # number of integer regfile reads
system.cpu.int_regfile_writes               757766233                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads               990216760                       # number of misc regfile reads
system.cpu.misc_regfile_writes                4464092                       # number of misc regfile writes
system.cpu.icache.replacements                  14932                       # number of replacements
system.cpu.icache.tagsinuse               1085.088818                       # Cycle average of tags in use
system.cpu.icache.total_refs                113022367                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  16785                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                6733.533929                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1085.088818                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.529829                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.529829                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    113022367                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       113022367                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     113022367                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        113022367                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    113022367                       # number of overall hits
system.cpu.icache.overall_hits::total       113022367                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        20976                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         20976                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        20976                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          20976                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        20976                       # number of overall misses
system.cpu.icache.overall_misses::total         20976                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    467556999                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    467556999                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    467556999                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    467556999                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    467556999                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    467556999                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    113043343                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    113043343                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    113043343                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    113043343                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    113043343                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    113043343                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000186                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000186                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000186                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000186                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000186                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000186                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22290.093392                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22290.093392                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22290.093392                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22290.093392                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22290.093392                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22290.093392                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1102                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    91.833333                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4107                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         4107                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         4107                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         4107                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         4107                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         4107                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16869                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        16869                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        16869                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        16869                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        16869                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        16869                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    341781999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    341781999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    341781999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    341781999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    341781999                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    341781999                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000149                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000149                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000149                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000149                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000149                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000149                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20260.951983                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20260.951983                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20260.951983                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20260.951983                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20260.951983                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20260.951983                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                115429                       # number of replacements
system.cpu.l2cache.tagsinuse             26914.468199                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1780391                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                146682                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 12.137761                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          106781718500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 22891.161180                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    363.700346                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   3659.606672                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.698583                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.011099                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.111682                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.821364                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        13362                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       804051                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         817413                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1110628                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1110628                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           67                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           67                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       247445                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       247445                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        13362                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1051496                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1064858                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        13362                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1051496                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1064858                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3407                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        43491                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        46898                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           16                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           16                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       101307                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       101307                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3407                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       144798                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        148205                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3407                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       144798                       # number of overall misses
system.cpu.l2cache.overall_misses::total       148205                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    190701000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2548389999                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2739090999                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        46000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        46000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5385063000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5385063000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    190701000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7933452999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8124153999                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    190701000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7933452999                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8124153999                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        16769                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       847542                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       864311                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1110628                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1110628                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           83                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           83                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       348752                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       348752                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        16769                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1196294                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1213063                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        16769                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1196294                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1213063                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.203173                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051314                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.054261                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.192771                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.192771                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290484                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.290484                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.203173                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.121039                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.122174                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.203173                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.121039                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.122174                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55973.290285                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58595.801407                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 58405.283786                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         2875                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total         2875                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53155.882614                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53155.882614                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55973.290285                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54789.796813                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54817.003468                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55973.290285                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54789.796813                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54817.003468                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97624                       # number of writebacks
system.cpu.l2cache.writebacks::total            97624                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            7                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           22                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           29                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            7                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           29                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            7                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           29                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3400                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43469                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        46869                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101307                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       101307                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3400                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       144776                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       148176                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3400                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       144776                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       148176                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    147345791                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1992861298                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2140207089                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       160016                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       160016                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4096834986                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4096834986                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    147345791                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6089696284                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6237042075                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    147345791                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6089696284                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6237042075                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.202755                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051288                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054227                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.192771                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.192771                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290484                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290484                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.202755                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.121020                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.122150                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.202755                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.121020                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.122150                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43336.997353                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45845.574961                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45663.596172                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40439.801652                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40439.801652                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43336.997353                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42062.885312                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42092.120688                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43336.997353                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42062.885312                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42092.120688                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1192198                       # number of replacements
system.cpu.dcache.tagsinuse               4054.757782                       # Cycle average of tags in use
system.cpu.dcache.total_refs                191677610                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1196294                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 160.226173                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             4661028000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4054.757782                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.989931                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.989931                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    136219311                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       136219311                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     50992877                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       50992877                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      2233119                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      2233119                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      2232045                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      2232045                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     187212188                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        187212188                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    187212188                       # number of overall hits
system.cpu.dcache.overall_hits::total       187212188                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1693600                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1693600                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3246429                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3246429                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           39                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           39                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4940029                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4940029                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4940029                       # number of overall misses
system.cpu.dcache.overall_misses::total       4940029                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  25893319000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  25893319000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  58743058946                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  58743058946                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       632500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       632500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  84636377946                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  84636377946                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  84636377946                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  84636377946                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    137912911                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    137912911                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2233158                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      2233158                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      2232045                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      2232045                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    192152217                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    192152217                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    192152217                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    192152217                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012280                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.012280                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059854                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.059854                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000017                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000017                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025709                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025709                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025709                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025709                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15288.922414                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15288.922414                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18094.669234                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 18094.669234                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16217.948718                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16217.948718                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17132.769453                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17132.769453                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17132.769453                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17132.769453                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        16010                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        16009                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1643                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             605                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.744370                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    26.461157                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1110628                       # number of writebacks
system.cpu.dcache.writebacks::total           1110628                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       845499                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       845499                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2898153                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2898153                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           39                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           39                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3743652                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3743652                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3743652                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3743652                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848101                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       848101                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348276                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       348276                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1196377                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1196377                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1196377                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1196377                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11475197000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  11475197000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8257593997                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8257593997                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19732790997                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  19732790997                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19732790997                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  19732790997                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006150                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006150                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006421                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006421                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006226                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006226                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006226                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006226                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13530.460405                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13530.460405                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23709.913968                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23709.913968                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16493.789998                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16493.789998                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16493.789998                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16493.789998                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------