path: root/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.206007                       # Number of seconds simulated
sim_ticks                                206006891000                       # Number of ticks simulated
final_tick                               206006891000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  48397                       # Simulator instruction rate (inst/s)
host_op_rate                                    54519                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               19589283                       # Simulator tick rate (ticks/s)
host_mem_usage                                 261836                       # Number of bytes of host memory used
host_seconds                                 10516.31                       # Real time elapsed on the host
sim_insts                                   508955198                       # Number of instructions simulated
sim_ops                                     573341758                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            216256                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           9272640                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9488896                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       216256                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          216256                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6250240                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6250240                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3379                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             144885                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                148264                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97660                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97660                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst              1049751                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             45011310                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                46061061                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1049751                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1049751                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          30339956                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               30339956                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          30339956                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1049751                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            45011310                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               76401017                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        148265                       # Total number of read requests seen
system.physmem.writeReqs                        97660                       # Total number of write requests seen
system.physmem.cpureqs                         245934                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                      9488896                       # Total number of bytes read from memory
system.physmem.bytesWritten                   6250240                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                9488896                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                6250240                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                       70                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                  9                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                  9228                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                  9188                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                  9341                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                  8794                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                  9227                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                  8981                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                  9254                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                  9466                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                  9155                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 10302                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                 9694                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                 9707                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                 9134                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                 8959                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                 9019                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                 8746                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  5978                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  6111                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  6105                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  5940                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  6130                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  5961                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  6031                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  6368                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  5968                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  6669                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 6289                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 6316                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 6051                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 6056                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 5913                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 5774                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    206006873500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  148265                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  97660                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                    9                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    138270                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      9286                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       558                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        72                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      4241                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      4247                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     1631933240                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                4708845240                       # Sum of mem lat for all requests
system.physmem.totBusLat                    592780000                       # Total cycles spent in databus access
system.physmem.totBankLat                  2484132000                       # Total cycles spent in bank access
system.physmem.avgQLat                       11012.07                       # Average queueing delay per request
system.physmem.avgBankLat                    16762.59                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  31774.66                       # Average memory access latency
system.physmem.avgRdBW                          46.06                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                          30.34                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  46.06                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                  30.34                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.48                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.02                       # Average read queue length over time
system.physmem.avgWrQLen                         8.58                       # Average write queue length over time
system.physmem.readRowHits                     128622                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     35037                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   86.79                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  35.88                       # Row buffer hit rate for writes
system.physmem.avgGap                       837681.71                       # Average gap between requests
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  548                       # Number of system calls
system.cpu.numCycles                        412013783                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                182073557                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          142374329                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            7271583                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              93640941                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 88714986                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                 12682930                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect              115717                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          117168420                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      763090504                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   182073557                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          101397916                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     170904146                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                35690489                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               89173012                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   22                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           387                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           48                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 113064693                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2443926                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          404864320                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.113664                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             2.961425                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                233972788     57.79%     57.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 14182494      3.50%     61.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 22907477      5.66%     66.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 22746192      5.62%     72.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 20892499      5.16%     77.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 13088798      3.23%     80.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 13051042      3.22%     84.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 11993527      2.96%     87.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 52029503     12.85%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            404864320                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.441911                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.852099                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                127567795                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              83214346                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 161081773                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               5456100                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               27544306                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             26131693                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 76746                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              833046476                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                293832                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               27544306                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                135636368                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 9592122                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles       57998215                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 158294561                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              15798748                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              804356889                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1117                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                3056071                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               8809517                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              236                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           960228219                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3520047664                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3520046036                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              1628                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             672200251                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                288027968                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts            3037400                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts        3037395                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  48984020                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            170948465                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            74181775                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          27930048                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         15662241                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  757938362                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded             4467556                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 669004170                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1390745                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       187223839                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    479595431                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         746429                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     404864320                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.652416                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.728625                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           145294997     35.89%     35.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            75803785     18.72%     54.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            69074812     17.06%     71.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            53696610     13.26%     84.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            30882442      7.63%     92.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            16155264      3.99%     96.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             9314791      2.30%     98.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             3366855      0.83%     99.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1274764      0.31%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       404864320                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  478550      4.99%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.99% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                6548662     68.24%     73.23% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2569141     26.77%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             449957502     67.26%     67.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               383513      0.06%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 114      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            154129801     23.04%     90.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            64533237      9.65%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              669004170                       # Type of FU issued
system.cpu.iq.rate                           1.623742                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     9596353                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014344                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         1753859495                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         950436200                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    649651296                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 263                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                358                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              678600390                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     133                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          8560025                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     44175415                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        40342                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       810510                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     16577803                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        19533                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          4184                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               27544306                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 4979953                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                372702                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           763965600                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1116680                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             170948465                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             74181775                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts            2978814                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 218949                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 11431                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         810510                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4342934                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4004049                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8346983                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             659511571                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             150841037                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           9492599                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                       1559682                       # number of nop insts executed
system.cpu.iew.exec_refs                    214084743                       # number of memory reference insts executed
system.cpu.iew.exec_branches                139192858                       # Number of branches executed
system.cpu.iew.exec_stores                   63243706                       # Number of stores executed
system.cpu.iew.exec_rate                     1.600703                       # Inst execution rate
system.cpu.iew.wb_sent                      654626894                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     649651312                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 375421754                       # num instructions producing a value
system.cpu.iew.wb_consumers                 646280118                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.576771                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.580896                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       189306245                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls         3721127                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           7197604                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    377320014                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.523072                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.207570                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    165631141     43.90%     43.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    102377769     27.13%     71.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     33965417      9.00%     80.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     18834681      4.99%     85.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     16120892      4.27%     89.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7588494      2.01%     91.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      6947007      1.84%     93.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3071988      0.81%     93.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22782625      6.04%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    377320014                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            510299082                       # Number of instructions committed
system.cpu.commit.committedOps              574685642                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      184377022                       # Number of memory references committed
system.cpu.commit.loads                     126773050                       # Number of loads committed
system.cpu.commit.membars                     1488542                       # Number of memory barriers committed
system.cpu.commit.branches                  122291796                       # Number of branches committed
system.cpu.commit.fp_insts                         16                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 473701673                       # Number of committed integer instructions.
system.cpu.commit.function_calls              9757362                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              22782625                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1118522138                       # The number of ROB reads
system.cpu.rob.rob_writes                  1555649058                       # The number of ROB writes
system.cpu.timesIdled                          306506                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         7149463                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   508955198                       # Number of Instructions Simulated
system.cpu.committedOps                     573341758                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             508955198                       # Number of Instructions Simulated
system.cpu.cpi                               0.809529                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.809529                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.235287                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.235287                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               3078340491                       # number of integer regfile reads
system.cpu.int_regfile_writes               757780607                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
system.cpu.misc_regfile_reads               213817535                       # number of misc regfile reads
system.cpu.misc_regfile_writes                4464074                       # number of misc regfile writes
system.cpu.icache.replacements                  15034                       # number of replacements
system.cpu.icache.tagsinuse               1084.596639                       # Cycle average of tags in use
system.cpu.icache.total_refs                113043631                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  16888                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                6693.725189                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1084.596639                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.529588                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.529588                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    113043631                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       113043631                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     113043631                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        113043631                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    113043631                       # number of overall hits
system.cpu.icache.overall_hits::total       113043631                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        21062                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         21062                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        21062                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          21062                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        21062                       # number of overall misses
system.cpu.icache.overall_misses::total         21062                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    460496000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    460496000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    460496000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    460496000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    460496000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    460496000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    113064693                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    113064693                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    113064693                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    113064693                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    113064693                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    113064693                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000186                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000186                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000186                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000186                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000186                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000186                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21863.830595                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21863.830595                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21863.830595                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21863.830595                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21863.830595                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21863.830595                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1088                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    90.666667                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4099                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         4099                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         4099                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         4099                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         4099                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         4099                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16963                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        16963                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        16963                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        16963                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        16963                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        16963                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    340828000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    340828000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    340828000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    340828000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    340828000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    340828000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000150                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000150                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000150                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000150                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000150                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000150                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20092.436479                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20092.436479                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20092.436479                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20092.436479                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20092.436479                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20092.436479                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                115524                       # number of replacements
system.cpu.l2cache.tagsinuse             26913.844111                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1781016                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                146770                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                 12.134741                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          106794042500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 22881.724629                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst    362.646179                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   3669.473303                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.698295                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.011067                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.111983                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.821345                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        13496                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       804094                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         817590                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1110621                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1110621                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           66                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           66                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       247478                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       247478                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        13496                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1051572                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1065068                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        13496                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1051572                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1065068                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3384                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        43623                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        47007                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            9                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            9                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       101285                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       101285                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3384                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       144908                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        148292                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3384                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       144908                       # number of overall misses
system.cpu.l2cache.overall_misses::total       148292                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    188319500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2550766500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2739086000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5396872000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5396872000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    188319500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7947638500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8135958000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    188319500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7947638500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8135958000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        16880                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       847717                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       864597                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1110621                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1110621                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           75                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           75                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       348763                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       348763                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        16880                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1196480                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1213360                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        16880                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1196480                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1213360                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.200474                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.051459                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.054369                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.120000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.120000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.290412                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.290412                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200474                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.121112                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.122216                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200474                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.121112                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.122216                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55649.970449                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58472.972973                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 58269.747059                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53284.020339                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53284.020339                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55649.970449                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54846.098904                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 54864.443126                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55649.970449                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54846.098904                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 54864.443126                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97660                       # number of writebacks
system.cpu.l2cache.writebacks::total            97660                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           22                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           27                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           27                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           27                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3379                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        43601                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        46980                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            9                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            9                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101285                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       101285                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3379                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       144886                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       148265                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3379                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       144886                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       148265                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    144900235                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1993232927                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2138133162                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        90009                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        90009                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4109014892                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4109014892                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    144900235                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6102247819                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6247148054                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    144900235                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6102247819                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   6247148054                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.200178                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.051433                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.054337                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.120000                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.120000                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.290412                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.290412                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200178                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.121094                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.122194                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200178                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.121094                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.122194                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42882.579165                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45715.303021                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45511.561558                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40568.839335                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40568.839335                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42882.579165                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42117.580850                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42135.015371                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42882.579165                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42117.580850                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42135.015371                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1192383                       # number of replacements
system.cpu.dcache.tagsinuse               4054.755183                       # Cycle average of tags in use
system.cpu.dcache.total_refs                191684453                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1196479                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 160.207119                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             4661028000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4054.755183                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.989930                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.989930                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    136225611                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       136225611                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     50993519                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       50993519                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      2233068                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      2233068                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      2232036                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      2232036                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     187219130                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        187219130                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    187219130                       # number of overall hits
system.cpu.dcache.overall_hits::total       187219130                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1694816                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1694816                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      3245787                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      3245787                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           38                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           38                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4940603                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4940603                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4940603                       # number of overall misses
system.cpu.dcache.overall_misses::total       4940603                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  25904626000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  25904626000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  58849421949                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  58849421949                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       574000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       574000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  84754047949                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  84754047949                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  84754047949                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  84754047949                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    137920427                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    137920427                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2233106                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      2233106                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      2232036                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      2232036                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    192159733                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    192159733                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    192159733                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    192159733                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012288                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.012288                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.059842                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.059842                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000017                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000017                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025711                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025711                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025711                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025711                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15284.624408                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15284.624408                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18131.017824                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 18131.017824                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15105.263158                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15105.263158                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 17154.595896                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 17154.595896                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17154.595896                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 17154.595896                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        17486                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        15854                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1635                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             605                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.694801                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    26.204959                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1110621                       # number of writebacks
system.cpu.dcache.writebacks::total           1110621                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       846554                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       846554                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2897494                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      2897494                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           38                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           38                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      3744048                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      3744048                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      3744048                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      3744048                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       848262                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       848262                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       348293                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       348293                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1196555                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1196555                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1196555                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1196555                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  11478175000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  11478175000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8269727997                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8269727997                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  19747902997                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  19747902997                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  19747902997                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  19747902997                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006150                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006150                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006421                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006421                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006227                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006227                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006227                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006227                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13531.403033                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13531.403033                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23743.595183                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23743.595183                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16503.965966                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16503.965966                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16503.965966                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16503.965966                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------