path: root/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.459106                       # Number of seconds simulated
sim_ticks                                459105675500                       # Number of ticks simulated
final_tick                               459105675500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  97287                       # Simulator instruction rate (inst/s)
host_op_rate                                   179895                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               54016738                       # Simulator tick rate (ticks/s)
host_mem_usage                                 345252                       # Number of bytes of host memory used
host_seconds                                  8499.32                       # Real time elapsed on the host
sim_insts                                   826877109                       # Number of instructions simulated
sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            202240                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24471936                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24674176                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       202240                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          202240                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18788544                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18788544                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3160                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             382374                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                385534                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          293571                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               293571                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               440509                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             53303493                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                53744001                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          440509                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             440509                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          40924225                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               40924225                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          40924225                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              440509                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            53303493                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               94668226                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        385534                       # Number of read requests accepted
system.physmem.writeReqs                       293571                       # Number of write requests accepted
system.physmem.readBursts                      385534                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     293571                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24663936                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     10240                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18787328                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24674176                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18788544                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      160                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         133980                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24056                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26412                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24662                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24490                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23228                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23668                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24406                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24200                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23616                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23822                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24814                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24049                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23223                       # Per bank write bursts
system.physmem.perBankRdBursts::13              22960                       # Per bank write bursts
system.physmem.perBankRdBursts::14              23777                       # Per bank write bursts
system.physmem.perBankRdBursts::15              23991                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18528                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19813                       # Per bank write bursts
system.physmem.perBankWrBursts::2               18933                       # Per bank write bursts
system.physmem.perBankWrBursts::3               18904                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18032                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18409                       # Per bank write bursts
system.physmem.perBankWrBursts::6               18982                       # Per bank write bursts
system.physmem.perBankWrBursts::7               18937                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18536                       # Per bank write bursts
system.physmem.perBankWrBursts::9               18110                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18825                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17714                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17347                       # Per bank write bursts
system.physmem.perBankWrBursts::13              16962                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17712                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17808                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    459105568000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  385534                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 293571                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    380726                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4314                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                     13202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                     13293                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                     13312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                     13323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                     13320                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                     13319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                     13374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                     13373                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                     13375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     13406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    13420                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    13359                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    13363                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    13367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    13343                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    13321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    13314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    13309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    13330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    13311                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    13494                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    13282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       147523                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      294.532839                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     155.815987                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     442.359788                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64             63790     43.24%     43.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128            27848     18.88%     62.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192            12415      8.42%     70.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256             7114      4.82%     75.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320             4845      3.28%     78.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384             3608      2.45%     81.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448             2677      1.81%     82.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512             2233      1.51%     84.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576             1891      1.28%     85.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640             1571      1.06%     86.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704             1991      1.35%     88.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768             1204      0.82%     88.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832             1205      0.82%     89.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896             1076      0.73%     90.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960              955      0.65%     91.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024             927      0.63%     91.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088            1004      0.68%     92.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152            1138      0.77%     93.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216            1120      0.76%     93.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280             845      0.57%     94.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344             784      0.53%     95.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408            5236      3.55%     98.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472             318      0.22%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536             229      0.16%     98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600             157      0.11%     99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664             117      0.08%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728             103      0.07%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792              91      0.06%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856              87      0.06%     99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920              53      0.04%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984              53      0.04%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048              37      0.03%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112              48      0.03%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176              24      0.02%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240              28      0.02%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304              24      0.02%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368              28      0.02%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432              24      0.02%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496              15      0.01%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560              23      0.02%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624              31      0.02%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688              20      0.01%     99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752              27      0.02%     99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816              23      0.02%     99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880              23      0.02%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944              20      0.01%     99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008              23      0.02%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072              23      0.02%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136              19      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200              14      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264              18      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328              16      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392               9      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456              13      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520              16      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584              16      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648              15      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712               8      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776              10      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840               5      0.00%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904              11      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968               8      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032              10      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096               6      0.00%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160              14      0.01%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224              17      0.01%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288              34      0.02%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352               3      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416               7      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480               2      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544               6      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608               2      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672               3      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736               5      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800               6      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864               1      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928               6      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992               5      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056               6      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120               5      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184               2      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248               2      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312               4      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376               3      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440               6      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504               3      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568               1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632               3      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696               2      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760               4      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824               4      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888               6      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952               4      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016               7      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080               4      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144               1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208               2      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272              19      0.01%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336               2      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         147523                       # Bytes accessed per row activation
system.physmem.totQLat                     3823508500                       # Total ticks spent queuing
system.physmem.totMemAccLat               12080026000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1926870000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  6329647500                       # Total ticks spent accessing banks
system.physmem.avgQLat                        9921.55                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    16424.69                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31346.24                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          53.72                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          40.92                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       53.74                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       40.92                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.74                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.75                       # Average write queue length when enqueuing
system.physmem.readRowHits                     326967                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    204436                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   84.84                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  69.64                       # Row buffer hit rate for writes
system.physmem.avgGap                       676045.04                       # Average gap between requests
system.physmem.pageHitRate                      78.27                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               5.78                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     94668226                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              178706                       # Transaction distribution
system.membus.trans_dist::ReadResp             178706                       # Transaction distribution
system.membus.trans_dist::Writeback            293571                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           133980                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          133980                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206828                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206828                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1332599                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1332599                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1332599                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43462720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43462720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            43462720                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               43462720                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          3389205500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3898787780                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               205604659                       # Number of BP lookups
system.cpu.branchPred.condPredicted         205604659                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           9906655                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            117175952                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               114700451                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.887364                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                25061463                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1805826                       # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        918372988                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          167405307                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1131731622                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   205604659                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          139761914                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     352276692                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                71095438                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              305025706                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                47339                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        248116                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           42                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 162029256                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2531741                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          885941657                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.376715                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.323883                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                537736172     60.70%     60.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 23397075      2.64%     63.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 25259789      2.85%     66.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 27891024      3.15%     69.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 17747651      2.00%     71.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 22912562      2.59%     73.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 29424314      3.32%     77.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 26642726      3.01%     80.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                174930344     19.75%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            885941657                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.223879                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.232322                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                222573687                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             260132185                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 295357990                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              46939340                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               60938455                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2071381091                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                     5                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               60938455                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                256079146                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               115670707                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          18358                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 306659021                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             146575970                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2035220367                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 19921                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               24919931                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents             106353414                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2138170371                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5150798156                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3273538468                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             41295                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                524129517                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               1246                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           1179                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 346542949                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            495881862                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           194416479                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         195473768                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         54732552                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1975446731                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               13521                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1772053501                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            482535                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       441556981                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    735252947                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          12969                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     885941657                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.000192                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.883038                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           269231258     30.39%     30.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           151900240     17.15%     47.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           137366514     15.51%     63.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           131748871     14.87%     77.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            91701810     10.35%     88.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            55961984      6.32%     94.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            34425337      3.89%     98.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            11840706      1.34%     99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1764937      0.20%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       885941657                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 4931859     32.39%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.39% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                7680982     50.45%     82.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2612006     17.16%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2622482      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1165712605     65.78%     65.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               353084      0.02%     65.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               3880807      0.22%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   5      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            429261253     24.22%     90.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           170223265      9.61%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1772053501                       # Type of FU issued
system.cpu.iq.rate                           1.929558                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    15224847                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.008592                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4445741046                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2417220510                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1744818779                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               14995                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              52000                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         3560                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1784648801                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                    7065                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        172668148                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    111780722                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       387016                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       326982                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     45256293                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        15018                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           570                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               60938455                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                67998417                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               7163340                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1975460252                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            795198                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             495882879                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            194416479                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               3400                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                4461902                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 83950                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         326982                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        5904539                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4423611                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             10328150                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1752928715                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             424128579                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          19124786                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    590915769                       # number of memory reference insts executed
system.cpu.iew.exec_branches                167467646                       # Number of branches executed
system.cpu.iew.exec_stores                  166787190                       # Number of stores executed
system.cpu.iew.exec_rate                     1.908733                       # Inst execution rate
system.cpu.iew.wb_sent                     1749675549                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1744822339                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1324948168                       # num instructions producing a value
system.cpu.iew.wb_consumers                1945614075                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.899906                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.680992                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       446501460                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           9934679                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    825003202                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.853312                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.435859                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    333018307     40.37%     40.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    193164035     23.41%     63.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     63275385      7.67%     71.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     92552193     11.22%     82.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     24927805      3.02%     85.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     27507260      3.33%     89.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      9364368      1.14%     90.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     11367203      1.38%     91.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     69826646      8.46%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    825003202                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262343                       # Number of memory references committed
system.cpu.commit.loads                     384102157                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758583                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              69826646                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   2730666717                       # The number of ROB reads
system.cpu.rob.rob_writes                  4012080782                       # The number of ROB writes
system.cpu.timesIdled                         3354849                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        32431331                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             826877109                       # Number of Instructions Simulated
system.cpu.cpi                               1.110652                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.110652                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.900372                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.900372                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2716202384                       # number of integer regfile reads
system.cpu.int_regfile_writes              1420402354                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      3547                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       23                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 597198676                       # number of cc regfile reads
system.cpu.cc_regfile_writes                405403172                       # number of cc regfile writes
system.cpu.misc_regfile_reads               964659775                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               697995780                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        1904573                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1904572                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      2330749                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq       135378                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp       135378                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       771770                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       771770                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       149099                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7669617                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7818716                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       435968                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311347520                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      311783488                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         311783488                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus      8670336                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     4905098758                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     213898487                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3952694158                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.icache.tags.replacements              5304                       # number of replacements
system.cpu.icache.tags.tagsinuse          1036.579952                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           161882998                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              6874                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          23550.043352                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1036.579952                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.506143                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.506143                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1570                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           44                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          248                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1211                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.766602                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         324200798                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        324200798                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    161884991                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       161884991                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     161884991                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        161884991                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    161884991                       # number of overall hits
system.cpu.icache.overall_hits::total       161884991                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       144265                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        144265                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       144265                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         144265                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       144265                       # number of overall misses
system.cpu.icache.overall_misses::total        144265                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    939571727                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    939571727                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    939571727                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    939571727                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    939571727                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    939571727                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    162029256                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    162029256                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    162029256                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    162029256                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    162029256                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    162029256                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000890                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000890                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000890                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000890                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000890                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000890                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6512.818265                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  6512.818265                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  6512.818265                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  6512.818265                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  6512.818265                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  6512.818265                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          329                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    41.125000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1978                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1978                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1978                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1978                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1978                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1978                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       142287                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       142287                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       142287                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       142287                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       142287                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       142287                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    558890013                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    558890013                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    558890013                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    558890013                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    558890013                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    558890013                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000878                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000878                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000878                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000878                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000878                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000878                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3927.906365                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3927.906365                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3927.906365                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  3927.906365                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3927.906365                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  3927.906365                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           352852                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29667.815296                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3696724                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           385211                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             9.596621                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     199249645000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21119.878039                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   223.140988                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8324.796269                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.644528                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006810                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.254053                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.905390                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32359                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          241                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11704                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20331                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987518                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         41214649                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        41214649                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst         3652                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1586740                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1590392                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2330749                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2330749                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1423                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1423                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       564917                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       564917                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         3652                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2151657                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2155309                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         3652                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2151657                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2155309                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3161                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       175546                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       178707                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data       133955                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       133955                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       206853                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       206853                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3161                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       382399                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        385560                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3161                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       382399                       # number of overall misses
system.cpu.l2cache.overall_misses::total       385560                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    241484750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  13186181960                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  13427666710                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      6452723                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      6452723                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  15146167475                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  15146167475                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    241484750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  28332349435                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  28573834185                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    241484750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  28332349435                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  28573834185                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         6813                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1762286                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1769099                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2330749                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2330749                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       135378                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       135378                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       771770                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       771770                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         6813                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2534056                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2540869                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         6813                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2534056                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2540869                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.463966                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099613                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.101016                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989489                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989489                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268024                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.268024                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.463966                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.150904                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151743                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.463966                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.150904                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151743                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76395.049035                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.251615                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75137.888891                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    48.170826                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    48.170826                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73221.889337                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73221.889337                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76395.049035                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74091.065706                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74109.954832                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76395.049035                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74091.065706                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74109.954832                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       293571                       # number of writebacks
system.cpu.l2cache.writebacks::total           293571                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3161                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175546                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       178707                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       133955                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       133955                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206853                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       206853                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3161                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       382399                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       385560                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3161                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       382399                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       385560                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    201970750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10947076960                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  11149047710                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1342825429                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1342825429                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12520595025                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12520595025                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    201970750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23467671985                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23669642735                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    201970750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23467671985                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23669642735                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.463966                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099613                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101016                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989489                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989489                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268024                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268024                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.463966                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150904                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151743                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.463966                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150904                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151743                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63894.574502                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62360.161781                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62387.302736                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.451711                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.451711                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60528.950632                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60528.950632                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63894.574502                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61369.595593                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61390.296543                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63894.574502                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61369.595593                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61390.296543                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           2529960                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4088.243311                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           395939715                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2534056                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            156.247421                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1794365000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4088.243311                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998106                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998106                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           17                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          739                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3316                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         801001196                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        801001196                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    247190433                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       247190433                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148236290                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148236290                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     395426723                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        395426723                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    395426723                       # number of overall hits
system.cpu.dcache.overall_hits::total       395426723                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2882935                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2882935                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       923912                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       923912                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3806847                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3806847                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3806847                       # number of overall misses
system.cpu.dcache.overall_misses::total       3806847                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  58045368359                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  58045368359                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  26823619163                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  26823619163                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  84868987522                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  84868987522                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  84868987522                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  84868987522                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    250073368                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    250073368                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    399233570                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    399233570                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    399233570                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    399233570                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011528                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011528                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006194                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006194                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009535                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009535                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009535                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009535                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20134.123162                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20134.123162                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29032.655884                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29032.655884                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22293.774224                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22293.774224                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22293.774224                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22293.774224                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         6982                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               660                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.578788                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2330749                       # number of writebacks
system.cpu.dcache.writebacks::total           2330749                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1120394                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1120394                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17019                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        17019                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1137413                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1137413                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1137413                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1137413                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762541                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1762541                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       906893                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       906893                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2669434                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2669434                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2669434                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2669434                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30851541255                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  30851541255                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24700633087                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  24700633087                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55552174342                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  55552174342                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55552174342                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  55552174342                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007048                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007048                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006080                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006080                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006686                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006686                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.013385                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.013385                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27236.546193                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27236.546193                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20810.469314                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20810.469314                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20810.469314                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20810.469314                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------