path: root/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.487051                       # Number of seconds simulated
sim_ticks                                487050729500                       # Number of ticks simulated
final_tick                               487050729500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 151835                       # Simulator instruction rate (inst/s)
host_op_rate                                   280970                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               89437473                       # Simulator tick rate (ticks/s)
host_mem_usage                                 318556                       # Number of bytes of host memory used
host_seconds                                  5445.71                       # Real time elapsed on the host
sim_insts                                   826847303                       # Number of instructions simulated
sim_ops                                    1530082520                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            156352                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24658560                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24814912                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       156352                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          156352                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18911424                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18911424                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2443                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             385290                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                387733                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          295491                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               295491                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               321018                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             50628320                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50949338                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          321018                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             321018                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          38828448                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               38828448                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          38828448                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              321018                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            50628320                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               89777786                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        387733                       # Number of read requests accepted
system.physmem.writeReqs                       295491                       # Number of write requests accepted
system.physmem.readBursts                      387733                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     295491                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24795072                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     19840                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18909504                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24814912                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18911424                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      310                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24612                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26389                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24828                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24571                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23534                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23661                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24754                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24509                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23888                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23557                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24834                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24002                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23243                       # Per bank write bursts
system.physmem.perBankRdBursts::13              22894                       # Per bank write bursts
system.physmem.perBankRdBursts::14              23905                       # Per bank write bursts
system.physmem.perBankRdBursts::15              24242                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18972                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19954                       # Per bank write bursts
system.physmem.perBankWrBursts::2               19038                       # Per bank write bursts
system.physmem.perBankWrBursts::3               19006                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18208                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18444                       # Per bank write bursts
system.physmem.perBankWrBursts::6               19174                       # Per bank write bursts
system.physmem.perBankWrBursts::7               19116                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18744                       # Per bank write bursts
system.physmem.perBankWrBursts::9               17955                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18923                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17774                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17399                       # Per bank write bursts
system.physmem.perBankWrBursts::13              16985                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17804                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17965                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    487050613500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  387733                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 295491                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    381263                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      5754                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       361                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        34                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6088                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    17482                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    17661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    17684                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    17682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    17689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    17695                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    17698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    17697                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    17702                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    17729                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17712                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17704                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       146416                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      298.484100                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     176.719176                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     324.748192                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          52816     36.07%     36.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        41066     28.05%     64.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        13865      9.47%     73.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7498      5.12%     78.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         4985      3.40%     82.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         3806      2.60%     84.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         2894      1.98%     86.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2818      1.92%     88.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16668     11.38%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         146416                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17678                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        21.914866                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       18.161180                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      216.039339                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          17672     99.97%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            2      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17678                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17678                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.713486                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.686282                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.965426                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16              11315     64.01%     64.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                269      1.52%     65.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               5957     33.70%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                123      0.70%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 10      0.06%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                  3      0.02%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17678                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9794922250                       # Total ticks spent queuing
system.physmem.totMemAccLat               17059103500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1937115000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25282.24                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44032.24                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          50.91                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          38.82                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       50.95                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       38.83                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.70                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.40                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.30                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        20.96                       # Average write queue length when enqueuing
system.physmem.readRowHits                     316322                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    220133                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.65                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.50                       # Row buffer hit rate for writes
system.physmem.avgGap                       712871.05                       # Average gap between requests
system.physmem.pageHitRate                      78.55                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  538191780                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  286032945                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1405566120                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                792980640                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           13571251200.000004                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             8851881120                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              742850400                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       36305173020                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       16998972000                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy        84070895340                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             163568832135                       # Total energy per rank (pJ)
system.physmem_0.averagePower              335.835307                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           465691902250                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     1184996500                       # Time in different power states
system.physmem_0.memoryStateTime::REF      5763492000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   341808238000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN  44268234250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     14409717250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN  79616051500                       # Time in different power states
system.physmem_1.actEnergy                  507311280                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  269615775                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1360634100                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                749325780                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           13094905200.000004                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             8819547870                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              717418080                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       34208424030                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       16648938720                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy        85396744800                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             161777173725                       # Total energy per rank (pJ)
system.physmem_1.averagePower              332.156722                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           465831856000                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     1145526000                       # Time in different power states
system.physmem_1.memoryStateTime::REF      5561926000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   347456670000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN  43356567250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     14511269750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  75018770500                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups               299198029                       # Number of BP lookups
system.cpu.branchPred.condPredicted         299198029                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          24258277                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            226066805                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                40193400                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            4437789                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups       226066805                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits          118144411                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses        107922394                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted     11883156                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.workload.numSyscalls                   551                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        974101460                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          230169557                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1594277830                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   299198029                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          158337811                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     718471067                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                49469999                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                       2698                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                34945                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        480096                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles         4714                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles           69                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 216546560                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               6526632                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       8                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          973898145                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              3.063667                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.497102                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                481357803     49.43%     49.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 36544666      3.75%     53.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 36285723      3.73%     56.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 32866211      3.37%     60.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 28367371      2.91%     63.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 29577354      3.04%     66.23% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 39843150      4.09%     70.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 36876934      3.79%     74.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                252178933     25.89%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            973898145                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.307153                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.636665                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                166490369                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             388298779                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 313723542                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              80650456                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               24734999                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2751923456                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               24734999                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                202899221                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               199700520                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          14210                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 351959746                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             194589449                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2631585273                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                503822                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents              119585114                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               21729790                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               44646970                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2710512651                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            6600728549                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       4213051781                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           1976674                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1616961572                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps               1093551079                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts                884                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            794                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 367177164                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            608809294                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           243550763                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         252688912                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         75518257                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2418516015                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded              104540                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1999668107                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           3656750                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       888538035                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   1505526254                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         103988                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     973898145                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.053262                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.107501                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           345655298     35.49%     35.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           135232191     13.89%     49.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           129689064     13.32%     62.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           119012847     12.22%     74.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            97852872     10.05%     84.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            66913699      6.87%     91.83% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            45825912      4.71%     96.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            22646304      2.33%     98.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8            11069958      1.14%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       973898145                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                11137608     43.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     43.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11929198     46.06%     89.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2740827     10.58%     99.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead                 0      0.00%     99.64% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite            92541      0.36%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2900375      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1333719780     66.70%     66.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               357536      0.02%     66.86% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               4798411      0.24%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   4      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   1      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.10% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            471767183     23.59%     90.69% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           185670018      9.29%     99.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead               6      0.00%     99.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite         454793      0.02%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1999668107                       # Type of FU issued
system.cpu.iq.rate                           2.052833                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    25900174                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.012952                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5001578236                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3304560217                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1922724831                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             1213047                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            3212370                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       280288                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2022120560                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                  547346                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        180407023                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    224726218                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       356451                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       693943                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     94392568                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        33314                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           814                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               24734999                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               149663879                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               6607902                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2418620555                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1417513                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             608809531                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            243550763                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              36150                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1478128                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               4302509                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         693943                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        8551096                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect     21778410                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             30329506                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1944942401                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             457167604                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          54725706                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    635670117                       # number of memory reference insts executed
system.cpu.iew.exec_branches                185387955                       # Number of branches executed
system.cpu.iew.exec_stores                  178502513                       # Number of stores executed
system.cpu.iew.exec_rate                     1.996653                       # Inst execution rate
system.cpu.iew.wb_sent                     1933639401                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1923005119                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1456045504                       # num instructions producing a value
system.cpu.iew.wb_consumers                2200626785                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.974132                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.661650                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts       888612801                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          24293835                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    840170563                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.821157                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.461954                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    361187525     42.99%     42.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    184077910     21.91%     64.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     57677028      6.86%     71.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     87256558     10.39%     82.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     30345133      3.61%     85.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     26488854      3.15%     88.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     10500866      1.25%     90.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      9042630      1.08%     91.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     73594059      8.76%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    840170563                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826847303                       # Number of instructions committed
system.cpu.commit.committedOps             1530082520                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533241508                       # Number of memory references committed
system.cpu.commit.loads                     384083313                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149981740                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1527470225                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      2048202      0.13%      0.13% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        989691028     64.68%     64.82% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          306834      0.02%     64.84% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv          4794948      0.31%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.15% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       384083313     25.10%     90.25% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      149158195      9.75%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1530082520                       # Class of committed instruction
system.cpu.commit.bw_lim_events              73594059                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   3185271825                       # The number of ROB reads
system.cpu.rob.rob_writes                  4972894886                       # The number of ROB writes
system.cpu.timesIdled                            2025                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          203315                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826847303                       # Number of Instructions Simulated
system.cpu.committedOps                    1530082520                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.178091                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.178091                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.848831                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.848831                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2927263565                       # number of integer regfile reads
system.cpu.int_regfile_writes              1575987355                       # number of integer regfile writes
system.cpu.fp_regfile_reads                    281295                       # number of floating regfile reads
system.cpu.fp_regfile_writes                        5                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 617980900                       # number of cc regfile reads
system.cpu.cc_regfile_writes                419571241                       # number of cc regfile writes
system.cpu.misc_regfile_reads              1064489388                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           2545571                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4088.077195                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           420813077                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2549667                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            165.046289                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1863239500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4088.077195                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998066                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998066                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           22                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          606                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3449                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         850870799                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        850870799                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    272443625                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       272443625                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148366897                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148366897                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     420810522                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        420810522                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    420810522                       # number of overall hits
system.cpu.dcache.overall_hits::total       420810522                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2558730                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2558730                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       791314                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       791314                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3350044                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3350044                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3350044                       # number of overall misses
system.cpu.dcache.overall_misses::total       3350044                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  62817542000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  62817542000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  26367570500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  26367570500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  89185112500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  89185112500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  89185112500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  89185112500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    275002355                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    275002355                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149158211                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149158211                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    424160566                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    424160566                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    424160566                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    424160566                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009304                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.009304                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005305                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.005305                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.007898                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.007898                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.007898                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.007898                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24550.281585                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24550.281585                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33321.248581                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33321.248581                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26622.071979                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26622.071979                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26622.071979                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26622.071979                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         9991                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        13057                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               901                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              13                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.088790                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets  1004.384615                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      2337865                       # number of writebacks
system.cpu.dcache.writebacks::total           2337865                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       792851                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       792851                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         5950                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         5950                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       798801                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       798801                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       798801                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       798801                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1765879                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1765879                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       785364                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       785364                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2551243                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2551243                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2551243                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2551243                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  37626062000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  37626062000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  25475564000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  25475564000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63101626000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  63101626000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63101626000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  63101626000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006421                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006421                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005265                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005265                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006015                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006015                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006015                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006015                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21307.270770                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21307.270770                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.906499                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.906499                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24733.679230                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24733.679230                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24733.679230                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24733.679230                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements              3942                       # number of replacements
system.cpu.icache.tags.tagsinuse          1083.391017                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           216536709                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              5668                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          38203.371383                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1083.391017                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.529000                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.529000                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1726                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           80                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1564                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.842773                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         433100363                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        433100363                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    216536917                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       216536917                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     216536917                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        216536917                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    216536917                       # number of overall hits
system.cpu.icache.overall_hits::total       216536917                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         9643                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          9643                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         9643                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           9643                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         9643                       # number of overall misses
system.cpu.icache.overall_misses::total          9643                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    597021000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    597021000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    597021000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    597021000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    597021000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    597021000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    216546560                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    216546560                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    216546560                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    216546560                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    216546560                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    216546560                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000045                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000045                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61912.371669                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61912.371669                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61912.371669                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61912.371669                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61912.371669                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61912.371669                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1205                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs   100.416667                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks         3942                       # number of writebacks
system.cpu.icache.writebacks::total              3942                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2400                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2400                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2400                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2400                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2400                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2400                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7243                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         7243                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         7243                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         7243                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         7243                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         7243                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    398397500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    398397500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    398397500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    398397500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    398397500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    398397500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000033                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000033                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000033                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000033                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55004.487091                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55004.487091                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55004.487091                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 55004.487091                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55004.487091                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 55004.487091                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           356141                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        30645.512705                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            4711567                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           388909                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.114831                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      82679985000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks    70.320646                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   194.041770                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 30381.150290                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.002146                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005922                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.927159                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.935227                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32768                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          176                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1392                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        31134                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         41192837                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        41192837                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks      2337865                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      2337865                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks         3849                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total         3849                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1570                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1570                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       577208                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       577208                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3147                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         3147                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1587166                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1587166                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         3147                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2164374                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2167521                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         3147                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2164374                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2167521                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       206826                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       206826                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2443                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2443                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       178467                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       178467                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2443                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       385293                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        387736                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2443                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       385293                       # number of overall misses
system.cpu.l2cache.overall_misses::total       387736                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        30500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        30500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  18217457500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  18217457500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    351826000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    351826000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18259810000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  18259810000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    351826000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  36477267500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  36829093500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    351826000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  36477267500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  36829093500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      2337865                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      2337865                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks         3849                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total         3849                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1576                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1576                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       784034                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       784034                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5590                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         5590                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1765633                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1765633                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         5590                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2549667                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2555257                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         5590                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2549667                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2555257                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.003807                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.003807                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.263797                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.263797                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.437030                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.437030                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.101078                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.101078                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.437030                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.151115                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151741                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.437030                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.151115                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151741                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  5083.333333                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  5083.333333                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88081.080232                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88081.080232                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 144013.917315                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 144013.917315                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102314.769677                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 102314.769677                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 144013.917315                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94674.098673                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 94984.973023                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 144013.917315                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94674.098673                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 94984.973023                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks       295491                       # number of writebacks
system.cpu.l2cache.writebacks::total           295491                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           10                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total           10                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206826                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       206826                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2443                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2443                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       178467                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       178467                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2443                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       385293                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       387736                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2443                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       385293                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       387736                       # number of overall MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       120000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  16149197500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  16149197500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    327396000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    327396000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16475140000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16475140000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    327396000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  32624337500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  32951733500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    327396000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  32624337500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  32951733500                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.003807                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.003807                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.263797                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.263797                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.437030                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.437030                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.101078                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.101078                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.437030                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151115                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151741                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.437030                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151115                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151741                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        20000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        20000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78081.080232                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78081.080232                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 134013.917315                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 134013.917315                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92314.769677                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92314.769677                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 134013.917315                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84674.098673                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84984.973023                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 134013.917315                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84674.098673                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84984.973023                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      5107999                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2549734                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        19983                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         3565                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3558                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            7                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       1772876                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      2633356                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean         3942                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       268356                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         1576                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         1576                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       784034                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       784034                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq         7243                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1765633                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        16775                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7648057                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7664832                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       610048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312802048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          313412096                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      357794                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic              19017216                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      2914627                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.008154                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.089959                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2890867     99.18%     99.18% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              23753      0.81%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  7      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2914627                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4895855901                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      10867494                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3825288599                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests        740964                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       353722                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp             180910                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       295491                       # Transaction distribution
system.membus.trans_dist::CleanEvict            57731                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                9                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206823                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206823                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        180910                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1128697                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1128697                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1128697                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43726336                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43726336                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                43726336                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            387742                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  387742    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              387742                       # Request fanout histogram
system.membus.reqLayer0.occupancy          1998138500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2051606500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)

---------- End Simulation Statistics   ----------