path: root/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.459119                       # Number of seconds simulated
sim_ticks                                459118646000                       # Number of ticks simulated
final_tick                               459118646000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  66655                       # Simulator instruction rate (inst/s)
host_op_rate                                   123253                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               37009979                       # Simulator tick rate (ticks/s)
host_mem_usage                                 397004                       # Number of bytes of host memory used
host_seconds                                 12405.27                       # Real time elapsed on the host
sim_insts                                   826877109                       # Number of instructions simulated
sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            202048                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24472064                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24674112                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       202048                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          202048                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18787264                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18787264                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3157                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             382376                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                385533                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          293551                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               293551                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               440078                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             53302266                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                53742344                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          440078                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             440078                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          40920281                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               40920281                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          40920281                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              440078                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            53302266                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               94662625                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        385533                       # Number of read requests accepted
system.physmem.writeReqs                       293551                       # Number of write requests accepted
system.physmem.readBursts                      385533                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     293551                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24663104                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     11008                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18787008                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24674112                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18787264                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      172                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         134286                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24058                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26419                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24669                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24489                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23234                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23657                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24395                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24194                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23609                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23827                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24795                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24049                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23230                       # Per bank write bursts
system.physmem.perBankRdBursts::13              22964                       # Per bank write bursts
system.physmem.perBankRdBursts::14              23781                       # Per bank write bursts
system.physmem.perBankRdBursts::15              23991                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18530                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19817                       # Per bank write bursts
system.physmem.perBankWrBursts::2               18937                       # Per bank write bursts
system.physmem.perBankWrBursts::3               18901                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18031                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18405                       # Per bank write bursts
system.physmem.perBankWrBursts::6               18977                       # Per bank write bursts
system.physmem.perBankWrBursts::7               18937                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18537                       # Per bank write bursts
system.physmem.perBankWrBursts::9               18113                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18820                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17706                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17343                       # Per bank write bursts
system.physmem.perBankWrBursts::13              16958                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17714                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17821                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    459118532000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  385533                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 293551                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    380740                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4302                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       283                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        32                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                     13202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                     13291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                     13315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                     13330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                     13327                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                     13318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                     13375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                     13367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                     13375                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     13396                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    13419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    13353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    13357                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    13368                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    13341                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    13319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    13314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    13315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    13324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    13309                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    13490                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    13282                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       147556                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      294.463932                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     155.686360                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     443.719039                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64             63845     43.27%     43.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128            27907     18.91%     62.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192            12368      8.38%     70.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256             7167      4.86%     75.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320             4813      3.26%     78.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384             3571      2.42%     81.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448             2697      1.83%     82.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512             2226      1.51%     84.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576             1892      1.28%     85.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640             1575      1.07%     86.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704             1962      1.33%     88.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768             1193      0.81%     88.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832             1191      0.81%     89.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896             1073      0.73%     90.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960              940      0.64%     91.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024             929      0.63%     91.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088            1014      0.69%     92.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152            1122      0.76%     93.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216            1123      0.76%     93.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280             892      0.60%     94.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344             768      0.52%     95.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408            5249      3.56%     98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472             304      0.21%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536             220      0.15%     98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600             176      0.12%     99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664             127      0.09%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728              88      0.06%     99.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792              94      0.06%     99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856              86      0.06%     99.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920              56      0.04%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984              55      0.04%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048              48      0.03%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112              43      0.03%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176              26      0.02%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240              35      0.02%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304              32      0.02%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368              24      0.02%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432              27      0.02%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496              18      0.01%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560              18      0.01%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624              24      0.02%     99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688              20      0.01%     99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752              23      0.02%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816              17      0.01%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880              18      0.01%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944              20      0.01%     99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008              16      0.01%     99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072              19      0.01%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136              14      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200              17      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264              12      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328              19      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392               5      0.00%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456              18      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520              12      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584               8      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648              14      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712              10      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776              15      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840               9      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904               9      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968              11      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032              10      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096              12      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160              14      0.01%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224              20      0.01%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288              31      0.02%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352               4      0.00%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416              10      0.01%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480               3      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544               5      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608               2      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672               6      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736               6      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800               2      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864               4      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928               2      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992               4      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056               3      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120               3      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184               4      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312               6      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376               1      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440               5      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504               3      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568               3      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632               2      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696               4      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760               6      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824               2      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888               9      0.01%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952               3      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016              11      0.01%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080               4      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144               1      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208               3      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272              19      0.01%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336               3      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         147556                       # Bytes accessed per row activation
system.physmem.totQLat                     3828283250                       # Total ticks spent queuing
system.physmem.totMemAccLat               12084928250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1926805000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  6329840000                       # Total ticks spent accessing banks
system.physmem.avgQLat                        9934.28                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    16425.74                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31360.02                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          53.72                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          40.92                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       53.74                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       40.92                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.74                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.64                       # Average write queue length when enqueuing
system.physmem.readRowHits                     326971                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    204381                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   84.85                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  69.62                       # Row buffer hit rate for writes
system.physmem.avgGap                       676085.04                       # Average gap between requests
system.physmem.pageHitRate                      78.27                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               5.79                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     94662625                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              178699                       # Transaction distribution
system.membus.trans_dist::ReadResp             178699                       # Transaction distribution
system.membus.trans_dist::Writeback            293551                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           134286                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          134286                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206834                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206834                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1333189                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1333189                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1333189                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43461376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43461376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            43461376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               43461376                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          3389612000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3899599974                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               205593718                       # Number of BP lookups
system.cpu.branchPred.condPredicted         205593718                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           9903647                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            117157105                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               114691543                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.895508                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                25059747                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1804675                       # Number of incorrect RAS predictions.
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        918398587                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          167393029                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1131661435                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   205593718                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          139751290                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     352253008                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                71076779                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              305103735                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                48807                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        255424                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           42                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 162015300                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2531137                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          885975121                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.376486                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.323818                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                537792455     60.70%     60.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 23395629      2.64%     63.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 25258320      2.85%     66.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 27887801      3.15%     69.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 17745441      2.00%     71.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 22910084      2.59%     73.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 29420868      3.32%     77.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 26641357      3.01%     80.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                174923166     19.74%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            885975121                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.223861                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.232212                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                222542151                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             260234378                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 295346908                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              46930608                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               60921076                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2071264981                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                     1                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               60921076                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                256051169                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               115707666                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          18212                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 306637897                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             146639101                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2035099231                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 19841                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               24966361                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents             106369922                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2138037437                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5150524594                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3273371991                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             41733                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                523996583                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               1255                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           1189                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 346554163                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            495859665                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           194411587                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         195293101                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         54696349                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1975355646                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               13955                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1772015968                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            483793                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       441457587                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    735091170                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          13403                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     885975121                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.000074                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.882925                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           269258289     30.39%     30.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           151881714     17.14%     47.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           137407528     15.51%     63.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           131753954     14.87%     77.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            91677002     10.35%     88.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            55986071      6.32%     94.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            34414851      3.88%     98.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            11835829      1.34%     99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1759883      0.20%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       885975121                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 4932504     32.46%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                7653540     50.37%     82.83% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2609071     17.17%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2623104      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1165669250     65.78%     65.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               353281      0.02%     65.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               3880805      0.22%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  50      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            429265174     24.22%     90.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           170224304      9.61%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1772015968                       # Type of FU issued
system.cpu.iq.rate                           1.929463                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    15195115                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.008575                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4445670799                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2417030484                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1744778187                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               15166                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              51932                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         3516                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1784580890                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                    7089                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        172585161                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    111758592                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       386790                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       327293                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     45251401                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        14735                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           596                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               60921076                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                68026001                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               7165661                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1975369601                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            781836                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             495860749                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            194411587                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               3446                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                4462926                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 83952                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         327293                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        5902213                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4423139                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             10325352                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1752891418                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             424133385                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          19124550                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    590919865                       # number of memory reference insts executed
system.cpu.iew.exec_branches                167459905                       # Number of branches executed
system.cpu.iew.exec_stores                  166786480                       # Number of stores executed
system.cpu.iew.exec_rate                     1.908639                       # Inst execution rate
system.cpu.iew.wb_sent                     1749637243                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1744781703                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1324895228                       # num instructions producing a value
system.cpu.iew.wb_consumers                1945542332                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.899809                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.680990                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       446410033                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           9933076                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    825054045                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.853198                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.435700                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    333030107     40.36%     40.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    193187610     23.42%     63.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     63292581      7.67%     71.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     92556987     11.22%     82.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     24936073      3.02%     85.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     27503514      3.33%     89.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      9360719      1.13%     90.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     11372840      1.38%     91.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     69813614      8.46%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    825054045                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262343                       # Number of memory references committed
system.cpu.commit.loads                     384102157                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758583                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              69813614                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   2730639165                       # The number of ROB reads
system.cpu.rob.rob_writes                  4011880242                       # The number of ROB writes
system.cpu.timesIdled                         3355901                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        32423466                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             826877109                       # Number of Instructions Simulated
system.cpu.cpi                               1.110683                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.110683                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.900347                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.900347                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2716194969                       # number of integer regfile reads
system.cpu.int_regfile_writes              1420370160                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      3538                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       76                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 597194910                       # number of cc regfile reads
system.cpu.cc_regfile_writes                405402169                       # number of cc regfile writes
system.cpu.misc_regfile_reads               964642327                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               698022201                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        1904986                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1904985                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      2330749                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq       135709                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp       135709                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       771688                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       771688                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       149463                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7670245                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7819708                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       436992                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311346432                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      311783424                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         311783424                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus      8691584                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     4905579957                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     214416742                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3952860716                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.icache.tags.replacements              5299                       # number of replacements
system.cpu.icache.tags.tagsinuse          1035.961197                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           161868793                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              6888                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          23500.115128                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1035.961197                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.505840                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.505840                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1589                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          245                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1238                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.775879                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         324173234                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        324173234                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    161870665                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       161870665                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     161870665                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        161870665                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    161870665                       # number of overall hits
system.cpu.icache.overall_hits::total       161870665                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       144635                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        144635                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       144635                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         144635                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       144635                       # number of overall misses
system.cpu.icache.overall_misses::total        144635                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    939845985                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    939845985                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    939845985                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    939845985                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    939845985                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    939845985                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    162015300                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    162015300                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    162015300                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    162015300                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    162015300                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    162015300                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000893                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000893                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000893                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000893                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000893                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000893                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6498.053618                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  6498.053618                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  6498.053618                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  6498.053618                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  6498.053618                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  6498.053618                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          251                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    41.833333                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2000                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2000                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2000                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2000                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2000                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2000                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       142635                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       142635                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       142635                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       142635                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       142635                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       142635                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    558603007                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    558603007                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    558603007                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    558603007                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    558603007                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    558603007                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000880                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000880                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000880                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000880                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000880                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000880                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3916.310912                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3916.310912                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3916.310912                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  3916.310912                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3916.310912                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  3916.310912                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           352851                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29668.075307                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3697142                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           385214                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             9.597631                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     199249645000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21122.585790                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   223.642071                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8321.847447                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.644610                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006825                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.253963                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.905398                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32363                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           77                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          239                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11704                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20343                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987640                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         41217237                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        41217237                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst         3670                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1586809                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1590479                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2330749                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2330749                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1446                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1446                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       564831                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       564831                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         3670                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2151640                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2155310                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         3670                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2151640                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2155310                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3159                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       175542                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       178701                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data       134263                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       134263                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       206857                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       206857                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3159                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       382399                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        385558                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3159                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       382399                       # number of overall misses
system.cpu.l2cache.overall_misses::total       385558                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    240297250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  13188147460                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  13428444710                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      6534219                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      6534219                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  15150269977                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  15150269977                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    240297250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  28338417437                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  28578714687                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    240297250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  28338417437                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  28578714687                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         6829                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1762351                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1769180                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2330749                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2330749                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       135709                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       135709                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       771688                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       771688                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         6829                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2534039                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2540868                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         6829                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2534039                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2540868                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.462586                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099607                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.101008                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989345                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989345                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268058                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.268058                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.462586                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.150905                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151743                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.462586                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.150905                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151743                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76067.505540                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75128.159985                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75144.765334                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    48.667310                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    48.667310                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73240.305994                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73240.305994                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76067.505540                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74106.933954                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74122.997544                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76067.505540                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74106.933954                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74122.997544                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       293551                       # number of writebacks
system.cpu.l2cache.writebacks::total           293551                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3158                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175542                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       178700                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       134263                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       134263                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206857                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       206857                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3158                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       382399                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       385557                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3158                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       382399                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       385557                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    200687250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10949056460                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  11149743710                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1346042939                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1346042939                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12524505023                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12524505023                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    200687250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23473561483                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23674248733                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    200687250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23473561483                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23674248733                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.462440                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099607                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101007                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989345                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989345                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268058                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268058                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.462440                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150905                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151742                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.462440                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150905                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151742                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63548.844205                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62372.859259                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62393.641354                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.419803                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.419803                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60546.682119                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60546.682119                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63548.844205                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61384.997040                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61402.720565                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63548.844205                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61384.997040                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.720565                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           2529943                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4088.243531                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           396026298                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2534039                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            156.282637                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1794365000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4088.243531                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998106                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998106                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          730                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3318                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         801176347                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        801176347                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    247278807                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       247278807                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148236045                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148236045                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     395514852                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        395514852                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    395514852                       # number of overall hits
system.cpu.dcache.overall_hits::total       395514852                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2882145                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2882145                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       924157                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       924157                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3806302                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3806302                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3806302                       # number of overall misses
system.cpu.dcache.overall_misses::total       3806302                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  58050756258                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  58050756258                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  26834846719                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  26834846719                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  84885602977                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  84885602977                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  84885602977                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  84885602977                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    250160952                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    250160952                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    399321154                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    399321154                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    399321154                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    399321154                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011521                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011521                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006196                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006196                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009532                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009532                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009532                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009532                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20141.511360                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20141.511360                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29037.108109                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29037.108109                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22301.331575                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22301.331575                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22301.331575                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22301.331575                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         7238                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               664                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.900602                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2330749                       # number of writebacks
system.cpu.dcache.writebacks::total           2330749                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1119535                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1119535                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17020                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        17020                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1136555                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1136555                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1136555                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1136555                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762610                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1762610                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       907137                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       907137                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2669747                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2669747                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2669747                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2669747                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30854243503                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  30854243503                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24711423781                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  24711423781                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55565667284                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  55565667284                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55565667284                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  55565667284                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007046                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007046                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006082                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006082                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006686                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006686                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006686                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.861259                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.861259                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27241.115489                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27241.115489                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.083518                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.083518                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.083518                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.083518                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------