path: root/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.455715                       # Number of seconds simulated
sim_ticks                                455715234500                       # Number of ticks simulated
final_tick                               455715234500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  71545                       # Simulator instruction rate (inst/s)
host_op_rate                                   132294                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               39430208                       # Simulator tick rate (ticks/s)
host_mem_usage                                 421584                       # Number of bytes of host memory used
host_seconds                                 11557.52                       # Real time elapsed on the host
sim_insts                                   826877109                       # Number of instructions simulated
sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            225856                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24534720                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24760576                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       225856                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          225856                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18815424                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18815424                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3529                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             383355                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                386884                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          293991                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               293991                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               495608                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             53837831                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                54333439                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          495608                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             495608                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          41287678                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               41287678                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          41287678                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              495608                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            53837831                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               95621118                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        386885                       # Number of read requests accepted
system.physmem.writeReqs                       293991                       # Number of write requests accepted
system.physmem.readBursts                      386885                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     293991                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24739328                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     21248                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18814144                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24760640                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18815424                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      332                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         191853                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24085                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26442                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24611                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24606                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23306                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23756                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24486                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24652                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23681                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23594                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24798                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24077                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23369                       # Per bank write bursts
system.physmem.perBankRdBursts::13              23004                       # Per bank write bursts
system.physmem.perBankRdBursts::14              24109                       # Per bank write bursts
system.physmem.perBankRdBursts::15              23976                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18564                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19853                       # Per bank write bursts
system.physmem.perBankWrBursts::2               18919                       # Per bank write bursts
system.physmem.perBankWrBursts::3               18930                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18043                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18450                       # Per bank write bursts
system.physmem.perBankWrBursts::6               18985                       # Per bank write bursts
system.physmem.perBankWrBursts::7               19190                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18567                       # Per bank write bursts
system.physmem.perBankWrBursts::9               17917                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18839                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17726                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17379                       # Per bank write bursts
system.physmem.perBankWrBursts::13              16983                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17822                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17804                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    455715219000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  386885                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 293991                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    381599                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4552                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       347                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        43                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6246                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6677                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    16930                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    17476                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    17572                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    17558                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17557                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17577                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17595                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    17611                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    17644                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    17593                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    17697                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    17591                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    17646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17825                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17535                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17475                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       147989                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      294.299928                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     173.923079                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     321.799681                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          54958     37.14%     37.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        40521     27.38%     64.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        13835      9.35%     73.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7266      4.91%     78.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         5442      3.68%     82.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         4031      2.72%     85.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         3118      2.11%     87.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2726      1.84%     89.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16092     10.87%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         147989                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17431                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        22.176123                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      209.527519                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          17419     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            7      0.04%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            3      0.02%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17431                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17430                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.865060                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.791911                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.512995                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           17223     98.81%     98.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             149      0.85%     99.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              30      0.17%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31               9      0.05%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               3      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               1      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               3      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67               1      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               2      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17430                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4293065000                       # Total ticks spent queuing
system.physmem.totMemAccLat               11540915000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1932760000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11106.02                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      4999.99                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29855.97                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          54.29                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          41.28                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       54.33                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       41.29                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.75                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.65                       # Average write queue length when enqueuing
system.physmem.readRowHits                     317463                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    215067                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.13                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.15                       # Row buffer hit rate for writes
system.physmem.avgGap                       669307.21                       # Average gap between requests
system.physmem.pageHitRate                      78.25                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  572420520                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  312332625                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1528355400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                977968080                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            29764999680                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            65726366265                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           215773632750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             314656075320                       # Total energy per rank (pJ)
system.physmem_0.averagePower              690.468461                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   358390621750                       # Time in different power states
system.physmem_0.memoryStateTime::REF     15217280000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     82106088250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  546247800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  298051875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1486602000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                926776080                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            29764999680                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            63297439515                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           217904270250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             314224387200                       # Total energy per rank (pJ)
system.physmem_1.averagePower              689.521182                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   361949321250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     15217280000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     78547312500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               231695087                       # Number of BP lookups
system.cpu.branchPred.condPredicted         231695087                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           9749161                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            132117764                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               129359921                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.912587                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                28019082                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1472513                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        911430498                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          186296226                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1278949517                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   231695087                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          157379003                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     713875771                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                20236911                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        843                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                99453                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        835728                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles         1660                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles           72                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 180582964                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2713511                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       2                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          911228208                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.609913                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.335178                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                500401689     54.92%     54.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 34125690      3.75%     58.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 33332463      3.66%     62.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 33617134      3.69%     66.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 27404429      3.01%     69.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 27784633      3.05%     72.06% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 37330287      4.10%     76.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 33792897      3.71%     79.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                183438986     20.13%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            911228208                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.254210                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.403233                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                127697766                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             450696701                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 239651398                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              83063888                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               10118455                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2233614820                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               10118455                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                159982570                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               230664398                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          40764                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 285690426                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             224731595                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2183551679                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                177689                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents              141075901                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               24311507                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               48530126                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2288986524                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5525749346                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3513986925                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             64934                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                674945670                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               3353                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           3126                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 428782866                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            530734595                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           210445129                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         240719653                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         72347559                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2112788093                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               24468                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1829137533                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            426447                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       579133879                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   1007575077                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          23916                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     911228208                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.007332                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.067633                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           325992359     35.78%     35.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           131250522     14.40%     50.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           120537234     13.23%     63.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           111169469     12.20%     75.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            91475128     10.04%     85.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            61217160      6.72%     92.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            43196755      4.74%     97.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            18979354      2.08%     99.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             7410227      0.81%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       911228208                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                11335968     42.56%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               12226894     45.90%     88.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3075179     11.54%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2719775      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1213037771     66.32%     66.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               388267      0.02%     66.49% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               3880871      0.21%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 112      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 48      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                 465      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            435424012     23.80%     90.50% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           173686212      9.50%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1829137533                       # Type of FU issued
system.cpu.iq.rate                           2.006886                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    26638041                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014563                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4596535787                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2692210314                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1799537822                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               31975                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              69900                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         6901                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1853040947                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   14852                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        185563330                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    146635930                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       210802                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       388472                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     61284943                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        18850                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           952                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               10118455                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               169584093                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              10386937                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2112812561                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            394512                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             530738087                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            210445129                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               7053                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                4503089                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3731660                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         388472                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        5744189                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4593759                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             10337948                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1808033307                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             429361199                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          21104226                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    599489274                       # number of memory reference insts executed
system.cpu.iew.exec_branches                171937546                       # Number of branches executed
system.cpu.iew.exec_stores                  170128075                       # Number of stores executed
system.cpu.iew.exec_rate                     1.983731                       # Inst execution rate
system.cpu.iew.wb_sent                     1804836297                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1799544723                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1369264226                       # num instructions producing a value
system.cpu.iew.wb_consumers                2092761334                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.974418                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.654286                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       584053108                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           9837261                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    832077003                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.837557                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.497071                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    362943344     43.62%     43.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    175693429     21.12%     64.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     57310072      6.89%     71.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     86390127     10.38%     82.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     27179123      3.27%     85.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     27109381      3.26%     88.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      9762579      1.17%     89.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      8845708      1.06%     90.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     76843240      9.24%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    832077003                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262343                       # Number of memory references committed
system.cpu.commit.loads                     384102157                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758583                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      1819099      0.12%      0.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        989721889     64.73%     64.85% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          306834      0.02%     64.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv          3878536      0.25%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       384102157     25.12%     90.24% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
system.cpu.commit.bw_lim_events              76843240                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   2868275572                       # The number of ROB reads
system.cpu.rob.rob_writes                  4305421890                       # The number of ROB writes
system.cpu.timesIdled                            2629                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          202290                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.102256                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.102256                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.907230                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.907230                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2763463473                       # number of integer regfile reads
system.cpu.int_regfile_writes              1467615781                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      7179                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      441                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 600951276                       # number of cc regfile reads
system.cpu.cc_regfile_writes                409693961                       # number of cc regfile writes
system.cpu.misc_regfile_reads               991720731                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2532518                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4088.661230                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           388324970                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2536614                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            153.087924                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1688557250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4088.661230                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998208                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998208                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          783                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3267                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         785768584                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        785768584                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    239673208                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       239673208                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148177372                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148177372                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     387850580                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        387850580                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    387850580                       # number of overall hits
system.cpu.dcache.overall_hits::total       387850580                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2782575                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2782575                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       982830                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       982830                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3765405                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3765405                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3765405                       # number of overall misses
system.cpu.dcache.overall_misses::total       3765405                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  60028359597                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  60028359597                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  31203952015                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  31203952015                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  91232311612                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  91232311612                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  91232311612                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  91232311612                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    242455783                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    242455783                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    391615985                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    391615985                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    391615985                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    391615985                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011477                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011477                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006589                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006589                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009615                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009615                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009615                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009615                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21572.952965                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21572.952965                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31749.083784                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31749.083784                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24229.083355                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24229.083355                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24229.083355                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24229.083355                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        10901                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            5                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1090                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    10.000917                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     2.500000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2331746                       # number of writebacks
system.cpu.dcache.writebacks::total           2331746                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1016736                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1016736                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18354                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        18354                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1035090                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1035090                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1035090                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1035090                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1765839                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1765839                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       964476                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       964476                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2730315                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2730315                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2730315                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2730315                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32758208252                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  32758208252                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29421929982                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  29421929982                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62180138234                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  62180138234                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62180138234                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  62180138234                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007283                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007283                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006466                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006466                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006972                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006972                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006972                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006972                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18551.073032                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18551.073032                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30505.611318                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30505.611318                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22773.979645                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22773.979645                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22773.979645                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22773.979645                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements              7158                       # number of replacements
system.cpu.icache.tags.tagsinuse          1086.852590                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           180374777                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              8766                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          20576.634383                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1086.852590                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.530690                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.530690                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1608                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           56                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          291                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1188                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         361368535                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        361368535                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    180377818                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       180377818                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     180377818                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        180377818                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    180377818                       # number of overall hits
system.cpu.icache.overall_hits::total       180377818                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       205146                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        205146                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       205146                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         205146                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       205146                       # number of overall misses
system.cpu.icache.overall_misses::total        205146                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1309293240                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1309293240                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1309293240                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1309293240                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1309293240                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1309293240                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    180582964                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    180582964                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    180582964                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    180582964                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    180582964                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    180582964                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001136                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.001136                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001136                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.001136                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001136                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.001136                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6382.250885                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  6382.250885                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  6382.250885                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  6382.250885                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  6382.250885                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  6382.250885                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1556                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                23                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    67.652174                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2537                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2537                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2537                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2537                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2537                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2537                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       202609                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       202609                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       202609                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       202609                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       202609                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       202609                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    890830010                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    890830010                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    890830010                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    890830010                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    890830010                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    890830010                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001122                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001122                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001122                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.001122                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001122                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.001122                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4396.793874                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4396.793874                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4396.793874                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  4396.793874                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4396.793874                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  4396.793874                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           354201                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29695.160220                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3700802                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           386532                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             9.574374                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     197848612000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21110.060927                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   253.708059                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8331.391234                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.644228                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007743                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.254254                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.906224                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32331                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          224                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11729                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20298                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.986664                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         41726644                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        41726644                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst         5259                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1589230                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1594489                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2331746                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2331746                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1880                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1880                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       563997                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       563997                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         5259                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2153227                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2158486                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         5259                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2153227                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2158486                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3532                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       176392                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       179924                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data       191821                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       191821                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       206995                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       206995                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3532                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       383387                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        386919                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3532                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       383387                       # number of overall misses
system.cpu.l2cache.overall_misses::total       386919                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    291122000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  14268096000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  14559218000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13253076                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     13253076                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16447945218                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16447945218                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    291122000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  30716041218                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  31007163218                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    291122000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  30716041218                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  31007163218                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         8791                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1765622                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1774413                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2331746                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2331746                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       193701                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       193701                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       770992                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       770992                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         8791                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2536614                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2545405                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         8791                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2536614                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2545405                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.401775                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099904                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.101399                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990294                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990294                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268479                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.268479                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.401775                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.151141                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.152007                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.401775                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.151141                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.152007                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82424.122310                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80888.566375                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80918.710122                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    69.090850                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    69.090850                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79460.591889                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79460.591889                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82424.122310                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80117.586715                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80138.641984                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82424.122310                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80117.586715                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80138.641984                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       293991                       # number of writebacks
system.cpu.l2cache.writebacks::total           293991                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3531                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       176392                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       179923                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       191821                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       191821                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206995                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       206995                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3531                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       383387                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       386918                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3531                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       383387                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       386918                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    246937500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  12060771500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  12307709000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3460977638                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3460977638                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13859464782                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13859464782                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    246937500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  25920236282                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  26167173782                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    246937500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  25920236282                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  26167173782                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.401661                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099904                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101399                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990294                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990294                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268479                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268479                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.401661                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151141                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.152006                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.401661                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151141                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.152006                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69934.154630                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68374.821420                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68405.423431                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18042.746300                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18042.746300                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66955.553429                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66955.553429                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69934.154630                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.542496                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67629.765950                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69934.154630                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.542496                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67629.765950                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        1968231                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1968229                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      2331746                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq       193701                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp       193701                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       770992                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       770992                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       211398                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7792376                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8003774                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       562496                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311575040                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          312137536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      193818                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      5264670                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            5264670    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5264670                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4991624303                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     304450990                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3984789765                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.membus.trans_dist::ReadReq              179922                       # Transaction distribution
system.membus.trans_dist::ReadResp             179921                       # Transaction distribution
system.membus.trans_dist::Writeback            293991                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           191853                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          191853                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206963                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206963                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1451466                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1451466                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1451466                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43576000                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43576000                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                43576000                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            872729                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  872729    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              872729                       # Request fanout histogram
system.membus.reqLayer0.occupancy          2240390129                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2431381451                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)

---------- End Simulation Statistics   ----------