blob: c15724aa43157960a0cbc7569061701392f51d1c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.458276 # Number of seconds simulated
sim_ticks 458276279000 # Number of ticks simulated
final_tick 458276279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 81967 # Simulator instruction rate (inst/s)
host_op_rate 151565 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 45427941 # Simulator tick rate (ticks/s)
host_mem_usage 343960 # Number of bytes of host memory used
host_seconds 10087.98 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24475520 # Number of bytes read from this memory
system.physmem.bytes_read::total 24678208 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 18791744 # Number of bytes written to this memory
system.physmem.bytes_written::total 18791744 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 382430 # Number of read requests responded to by this memory
system.physmem.num_reads::total 385597 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 293621 # Number of write requests responded to by this memory
system.physmem.num_writes::total 293621 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 442283 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 53407783 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 53850066 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 442283 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 442283 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 41005273 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 41005273 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 41005273 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 442283 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 53407783 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 94855339 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 385597 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 293621 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 385597 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 293621 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead 24678208 # Total number of bytes read from memory
system.physmem.bytesWritten 18791744 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 24678208 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 18791744 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 167 # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite 129454 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 24004 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 26368 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 24819 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 24535 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 23440 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 23690 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 24438 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 24255 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 23670 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 23840 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 24809 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 23982 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 23151 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 22850 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 23658 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 23921 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 18532 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 19819 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 18953 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 18919 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 18083 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 18410 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 18967 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 18941 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 18561 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 18114 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 18821 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 17718 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 17344 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 16935 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 17686 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 17818 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry
system.physmem.totGap 458276251500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 385597 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 293621 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 380795 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 4297 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 12731 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 12737 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 12740 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 12741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 12744 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 12749 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 12750 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 12753 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 125846 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 345.334329 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 162.235120 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 666.634247 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 53836 42.78% 42.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 23576 18.73% 61.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 10431 8.29% 69.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 6405 5.09% 74.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 4091 3.25% 78.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 2950 2.34% 80.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 2205 1.75% 82.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 1721 1.37% 83.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 1423 1.13% 84.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 1129 0.90% 85.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 1178 0.94% 86.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 1088 0.86% 87.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 719 0.57% 88.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 691 0.55% 88.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 593 0.47% 89.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 590 0.47% 89.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 543 0.43% 89.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 555 0.44% 90.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 625 0.50% 90.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 694 0.55% 91.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 625 0.50% 91.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 735 0.58% 92.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 6224 4.95% 97.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 501 0.40% 97.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 329 0.26% 98.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 262 0.21% 98.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729 235 0.19% 98.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793 154 0.12% 98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 168 0.13% 98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921 127 0.10% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 91 0.07% 98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 78 0.06% 98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 63 0.05% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 57 0.05% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 48 0.04% 99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 48 0.04% 99.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 32 0.03% 99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 31 0.02% 99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 34 0.03% 99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 24 0.02% 99.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 22 0.02% 99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 28 0.02% 99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945 15 0.01% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 11 0.01% 99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 26 0.02% 99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 10 0.01% 99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201 12 0.01% 99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265 9 0.01% 99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 11 0.01% 99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521 10 0.01% 99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 11 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 9 0.01% 99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841 9 0.01% 99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 4 0.00% 99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097 11 0.01% 99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 3 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 5 0.00% 99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 10 0.01% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417 5 0.00% 99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673 4 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737 4 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057 12 0.01% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 10 0.01% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505 9 0.01% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569 8 0.01% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889 5 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657 4 0.00% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7617 3 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745 3 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 3 0.00% 99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 376 0.30% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 125846 # Bytes accessed per row activation
system.physmem.totQLat 3013395500 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 11189631750 # Sum of mem lat for all requests
system.physmem.totBusLat 1927150000 # Total cycles spent in databus access
system.physmem.totBankLat 6249086250 # Total cycles spent in bank access
system.physmem.avgQLat 7818.27 # Average queueing delay per request
system.physmem.avgBankLat 16213.28 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 29031.55 # Average memory access latency
system.physmem.avgRdBW 53.85 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 53.85 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.74 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
system.physmem.avgWrQLen 10.13 # Average write queue length over time
system.physmem.readRowHits 346215 # Number of row buffer hits during reads
system.physmem.writeRowHits 206987 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 70.49 # Row buffer hit rate for writes
system.physmem.avgGap 674711.58 # Average gap between requests
system.membus.throughput 94855339 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 178753 # Transaction distribution
system.membus.trans_dist::ReadResp 178753 # Transaction distribution
system.membus.trans_dist::Writeback 293621 # Transaction distribution
system.membus.trans_dist::UpgradeReq 129454 # Transaction distribution
system.membus.trans_dist::UpgradeResp 129454 # Transaction distribution
system.membus.trans_dist::ReadExReq 206844 # Transaction distribution
system.membus.trans_dist::ReadExResp 206844 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1323723 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1323723 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1323723 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469952 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469952 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 43469952 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 43469952 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 3387419250 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 3898953053 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.branchPred.lookups 205598458 # Number of BP lookups
system.cpu.branchPred.condPredicted 205598458 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 9896380 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 117174051 # Number of BTB lookups
system.cpu.branchPred.BTBHits 114692881 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 97.882492 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 25059076 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1793638 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 916711426 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 167358741 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1131763090 # Number of instructions fetch has processed
system.cpu.fetch.Branches 205598458 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 139751957 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 352259726 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 71078928 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 303625713 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 47908 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 254198 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 162013852 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 2539166 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 884476430 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.380618 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.325214 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 536284008 60.63% 60.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 23384253 2.64% 63.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 25253496 2.86% 66.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 27902300 3.15% 69.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 17749201 2.01% 71.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 22913352 2.59% 73.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 29416028 3.33% 77.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 26647385 3.01% 80.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 174926407 19.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 884476430 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.224278 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.234590 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 222500802 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 258763432 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 295392395 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 46889742 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 60930059 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2071354254 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 60930059 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 255984410 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 114277740 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 18348 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 306680368 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 146585505 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2035184371 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 17660 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 24877077 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 106438010 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2138008878 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5150477195 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 3273486109 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 27867 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 523968024 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1260 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1188 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 346256555 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 495848123 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 194451746 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 195373810 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 54752041 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1975440933 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 14060 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1772196947 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 491373 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 441593338 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 734714175 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 13508 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 884476430 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.003668 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.883218 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 267871954 30.29% 30.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 151795933 17.16% 47.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 137193879 15.51% 62.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 131984117 14.92% 77.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 91584837 10.35% 88.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 55972472 6.33% 94.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 34407043 3.89% 98.45% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 11912621 1.35% 99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1753574 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 884476430 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 4900873 32.33% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.33% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 7664927 50.56% 82.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 2594883 17.12% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2622931 0.15% 0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1165806661 65.78% 65.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 353241 0.02% 65.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 3880883 0.22% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 429278261 24.22% 90.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 170254965 9.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1772196947 # Type of FU issued
system.cpu.iq.rate 1.933211 # Inst issue rate
system.cpu.iq.fu_busy_cnt 15160683 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.008555 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4444507102 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2417272272 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1744936391 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 15278 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 33048 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 3640 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1784727445 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7254 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 172555642 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 111746790 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 385650 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 328822 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 45291560 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 15317 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 60930059 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 66792766 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 7181188 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1975454993 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 789344 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 495848947 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 194451746 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 4469390 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 83563 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 328822 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 5897715 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 4420728 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 10318443 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1753033326 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 424140898 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 19163621 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 590949993 # number of memory reference insts executed
system.cpu.iew.exec_branches 167484534 # Number of branches executed
system.cpu.iew.exec_stores 166809095 # Number of stores executed
system.cpu.iew.exec_rate 1.912307 # Inst execution rate
system.cpu.iew.wb_sent 1749784390 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1744940031 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1325078811 # num instructions producing a value
system.cpu.iew.wb_consumers 1946006295 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.903478 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.680922 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 446495753 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 9924967 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 823546371 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.856591 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.436968 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 331540397 40.26% 40.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 193316161 23.47% 63.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 63109500 7.66% 71.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 92579702 11.24% 82.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 24975285 3.03% 85.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27432624 3.33% 89.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 9320772 1.13% 90.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 11449898 1.39% 91.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 69822032 8.48% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 823546371 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 533262343 # Number of memory references committed
system.cpu.commit.loads 384102157 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 149758583 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
system.cpu.commit.bw_lim_events 69822032 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2729208793 # The number of ROB reads
system.cpu.rob.rob_writes 4012058416 # The number of ROB writes
system.cpu.timesIdled 3349890 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 32234996 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
system.cpu.cpi 1.108643 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.108643 # CPI: Total CPI of All Threads
system.cpu.ipc 0.902004 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.902004 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 2716444328 # number of integer regfile reads
system.cpu.int_regfile_writes 1420478428 # number of integer regfile writes
system.cpu.fp_regfile_reads 3628 # number of floating regfile reads
system.cpu.fp_regfile_writes 22 # number of floating regfile writes
system.cpu.cc_regfile_reads 597234249 # number of cc regfile reads
system.cpu.cc_regfile_writes 405441134 # number of cc regfile writes
system.cpu.misc_regfile_reads 964696527 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.toL2Bus.throughput 698612009 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1899997 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1899996 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 2330686 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 130874 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 130874 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 771776 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 771776 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 144643 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7660372 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7805015 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437696 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311337920 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 311775616 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 311775616 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 8381696 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 4900939314 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 207374491 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3958743651 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.icache.tags.replacements 5318 # number of replacements
system.cpu.icache.tags.tagsinuse 1036.794557 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 161872030 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6894 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 23480.131999 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1036.794557 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.506247 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.506247 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 161874097 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 161874097 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 161874097 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 161874097 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 161874097 # number of overall hits
system.cpu.icache.overall_hits::total 161874097 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 139755 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 139755 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 139755 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 139755 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 139755 # number of overall misses
system.cpu.icache.overall_misses::total 139755 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 916174482 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 916174482 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 916174482 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 916174482 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 916174482 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 916174482 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 162013852 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 162013852 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 162013852 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 162013852 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 162013852 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 162013852 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000863 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000863 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000863 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000863 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000863 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000863 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6555.575700 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 6555.575700 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 6555.575700 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 6555.575700 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 1833 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 166.636364 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1951 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1951 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1951 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1951 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1951 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1951 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 137804 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 137804 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 137804 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 137804 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 137804 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 137804 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 553553258 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 553553258 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 553553258 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 553553258 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 553553258 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 553553258 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000851 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000851 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000851 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4016.960741 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4016.960741 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 352916 # number of replacements
system.cpu.l2cache.tags.tagsinuse 29674.078168 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3696976 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 385280 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 9.595556 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 199035325000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21118.733135 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 224.036414 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 8331.308620 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.644493 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006837 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.254251 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.905581 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 3672 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1586607 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1590279 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 2330686 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 2330686 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1446 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1446 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 564906 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 564906 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3672 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 2151513 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2155185 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 3672 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 2151513 # number of overall hits
system.cpu.l2cache.overall_hits::total 2155185 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3168 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 175586 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 178754 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 129428 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 129428 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 206870 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206870 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3168 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 382456 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 385624 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 382456 # number of overall misses
system.cpu.l2cache.overall_misses::total 385624 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245961000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13200679958 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 13446640958 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6462222 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 6462222 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14256875974 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 14256875974 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 245961000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 27457555932 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 27703516932 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 245961000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 27457555932 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 27703516932 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6840 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1762193 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1769033 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 2330686 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 2330686 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 130874 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 130874 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 771776 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 771776 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 6840 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2533969 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2540809 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 6840 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2533969 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2540809 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463158 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099641 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.101046 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988951 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988951 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268044 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.268044 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463158 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150932 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.151772 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463158 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150932 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.151772 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77639.204545 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75180.708929 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75224.280061 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.929088 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.929088 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68917.078233 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68917.078233 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71840.748843 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71840.748843 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 293621 # number of writebacks
system.cpu.l2cache.writebacks::total 293621 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3168 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175586 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 178754 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 129428 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 129428 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206870 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206870 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 382456 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 385624 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 382456 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 385624 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205953000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10947318958 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11153271958 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1297954472 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1297954472 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11628367526 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11628367526 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205953000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22575686484 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 22781639484 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205953000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22575686484 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 22781639484 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099641 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101046 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988951 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988951 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268044 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268044 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151772 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151772 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65010.416667 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62347.333831 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62394.530797 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10028.390086 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10028.390086 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56210.990119 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56210.990119 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 2529873 # number of replacements
system.cpu.dcache.tags.tagsinuse 4088.353795 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 396071280 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2533969 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 156.304706 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353795 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 247337709 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 247337709 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 148240799 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 148240799 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 395578508 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 395578508 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 395578508 # number of overall hits
system.cpu.dcache.overall_hits::total 395578508 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2867309 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2867309 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 919403 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 919403 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3786712 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3786712 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3786712 # number of overall misses
system.cpu.dcache.overall_misses::total 3786712 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57500595434 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 57500595434 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25821603651 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 25821603651 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 83322199085 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 83322199085 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 83322199085 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 83322199085 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250205018 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250205018 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 399365220 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 399365220 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 399365220 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 399365220 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011460 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.011460 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006164 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.006164 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009482 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009482 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009482 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009482 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.853782 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.853782 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28085.185333 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28085.185333 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22003.838445 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22003.838445 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 7384 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 704 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.488636 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 2330686 # number of writebacks
system.cpu.dcache.writebacks::total 2330686 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1104851 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1104851 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17019 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 17019 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1121870 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1121870 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1121870 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1121870 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762458 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1762458 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 902384 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 902384 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2664842 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2664842 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2664842 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2664842 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30865724250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 30865724250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23705880099 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 23705880099 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54571604349 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 54571604349 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54571604349 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 54571604349 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006050 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006050 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006673 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006673 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17512.884988 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17512.884988 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26270.279725 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26270.279725 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|