path: root/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.459341                       # Number of seconds simulated
sim_ticks                                459340600000                       # Number of ticks simulated
final_tick                               459340600000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  64463                       # Simulator instruction rate (inst/s)
host_op_rate                                   119200                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               35810129                       # Simulator tick rate (ticks/s)
host_mem_usage                                 391936                       # Number of bytes of host memory used
host_seconds                                 12827.11                       # Real time elapsed on the host
sim_insts                                   826877109                       # Number of instructions simulated
sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            203008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24478016                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24681024                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       203008                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          203008                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18788608                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18788608                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3172                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             382469                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                385641                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          293572                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               293572                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               441955                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             53289468                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                53731423                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          441955                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             441955                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          40903434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               40903434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          40903434                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              441955                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            53289468                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               94634857                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        385641                       # Number of read requests accepted
system.physmem.writeReqs                       293572                       # Number of write requests accepted
system.physmem.readBursts                      385641                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     293572                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24669632                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     11392                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18788480                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24681024                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18788608                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      178                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         135253                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24057                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26446                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24658                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24494                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23239                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23672                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24412                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24201                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23613                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23828                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24822                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24051                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23218                       # Per bank write bursts
system.physmem.perBankRdBursts::13              22963                       # Per bank write bursts
system.physmem.perBankRdBursts::14              23780                       # Per bank write bursts
system.physmem.perBankRdBursts::15              24009                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18526                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19824                       # Per bank write bursts
system.physmem.perBankWrBursts::2               18930                       # Per bank write bursts
system.physmem.perBankWrBursts::3               18895                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18030                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18409                       # Per bank write bursts
system.physmem.perBankWrBursts::6               18982                       # Per bank write bursts
system.physmem.perBankWrBursts::7               18942                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18537                       # Per bank write bursts
system.physmem.perBankWrBursts::9               18120                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18829                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17702                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17342                       # Per bank write bursts
system.physmem.perBankWrBursts::13              16954                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17718                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17830                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    459340574000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  385641                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 293572                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    380895                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4253                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       284                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                     13203                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                     13289                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                     13319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                     13330                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                     13323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                     13318                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                     13380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                     13367                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                     13383                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                     13400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                    13420                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                    13351                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                    13361                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                    13365                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                    13348                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    13319                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    13314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    13314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    13324                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    13314                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    13479                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    13297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       147621                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      294.388468                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     155.710774                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     443.499186                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64             63823     43.23%     43.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128            27954     18.94%     62.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192            12395      8.40%     70.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256             7134      4.83%     75.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320             4845      3.28%     78.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384             3604      2.44%     81.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448             2701      1.83%     82.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512             2191      1.48%     84.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576             1897      1.29%     85.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640             1561      1.06%     86.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704             2008      1.36%     88.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768             1215      0.82%     88.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832             1176      0.80%     89.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896             1069      0.72%     90.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960              885      0.60%     91.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024             912      0.62%     91.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088            1043      0.71%     92.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152            1161      0.79%     93.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216            1134      0.77%     93.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280             871      0.59%     94.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344             771      0.52%     95.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408            5235      3.55%     98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472             297      0.20%     98.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536             223      0.15%     98.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600             174      0.12%     99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664             140      0.09%     99.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728              99      0.07%     99.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792             107      0.07%     99.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856              67      0.05%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920              49      0.03%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984              50      0.03%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048              49      0.03%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112              40      0.03%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176              28      0.02%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240              31      0.02%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304              21      0.01%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368              22      0.01%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432              31      0.02%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496              30      0.02%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560              18      0.01%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624              24      0.02%     99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688              16      0.01%     99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752              18      0.01%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816              20      0.01%     99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880              17      0.01%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944              18      0.01%     99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008              17      0.01%     99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072              21      0.01%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136              13      0.01%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200              13      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264              16      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328              15      0.01%     99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392               9      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456              14      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520              12      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584              17      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648              16      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712               8      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776              10      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840               9      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904              11      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968               6      0.00%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032              17      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096               7      0.00%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160              17      0.01%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224              18      0.01%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288              37      0.03%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352               5      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416               5      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480               6      0.00%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544               5      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608               4      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672               3      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736               4      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800               1      0.00%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864               3      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928               5      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992               2      0.00%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056               8      0.01%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120               4      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184               3      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248               3      0.00%     99.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312               6      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376               3      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440               5      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504               5      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568               4      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632               1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696               4      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760               1      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824               2      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888               6      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952               3      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016              14      0.01%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080               3      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144               2      0.00%     99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272              19      0.01%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336               3      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         147621                       # Bytes accessed per row activation
system.physmem.totQLat                     3824316500                       # Total ticks spent queuing
system.physmem.totMemAccLat               12085472750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1927315000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  6333841250                       # Total ticks spent accessing banks
system.physmem.avgQLat                        9921.36                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    16431.77                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31353.13                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          53.71                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          40.90                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       53.73                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       40.90                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.74                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.23                       # Average write queue length when enqueuing
system.physmem.readRowHits                     326993                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    204419                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   84.83                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  69.63                       # Row buffer hit rate for writes
system.physmem.avgGap                       676283.54                       # Average gap between requests
system.physmem.pageHitRate                      78.26                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               5.85                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     94634857                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              178796                       # Transaction distribution
system.membus.trans_dist::ReadResp             178796                       # Transaction distribution
system.membus.trans_dist::Writeback            293572                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           135253                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          135253                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206845                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206845                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1335360                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1335360                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1335360                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43469632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total     43469632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            43469632                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               43469632                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          3391724500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
system.membus.respLayer1.occupancy         3901051256                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.8                       # Layer utilization (%)
system.cpu.branchPred.lookups               205617807                       # Number of BP lookups
system.cpu.branchPred.condPredicted         205617807                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           9908418                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            117215133                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               114724662                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.875299                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                25059559                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1805276                       # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        918840117                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          167454161                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1131890109                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   205617807                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          139784221                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     352321921                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                71123589                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              305412308                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                47848                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        248697                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           51                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 162055223                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2523762                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          886447009                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.375660                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.323512                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                538196407     60.71%     60.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 23398337      2.64%     63.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 25267875      2.85%     66.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 27893164      3.15%     69.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 17745237      2.00%     71.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 22915160      2.59%     73.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 29437572      3.32%     77.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 26645476      3.01%     80.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                174947781     19.74%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            886447009                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.223780                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.231868                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                222604172                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             260544811                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 295377211                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              46958792                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               60962023                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2071584997                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                     1                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               60962023                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                256124443                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               115849529                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          18111                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 306710232                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             146782671                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2035392094                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                 19900                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents               24933273                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents             106586441                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2138335278                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5151319538                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3273897775                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             39701                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                524294424                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               1242                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           1171                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 346564705                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            495938130                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           194456766                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         195343621                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         54992684                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1975627132                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               13244                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1772183771                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            484863                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       441729805                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    735457697                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          12692                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     886447009                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.999199                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.882883                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           269548828     30.41%     30.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           152175288     17.17%     47.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           137113127     15.47%     63.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           132050060     14.90%     77.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            91550725     10.33%     88.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            55998430      6.32%     94.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            34403840      3.88%     98.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            11839729      1.34%     99.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1766982      0.20%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       886447009                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 4936288     32.45%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     32.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                7665302     50.39%     82.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               2609145     17.15%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2622898      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1165798232     65.78%     65.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               353842      0.02%     65.95% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               3880856      0.22%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   5      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.17% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            429305841     24.22%     90.39% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           170222097      9.61%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1772183771                       # Type of FU issued
system.cpu.iq.rate                           1.928718                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    15210735                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.008583                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4446495646                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2417577635                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1744952561                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               14503                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              50594                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         3428                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1784764794                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                    6814                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        172654482                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    111836934                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       389891                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       330016                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     45296580                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        14646                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           570                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               60962023                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                68066484                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               7196875                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1975640376                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            789853                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             495939091                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            194456766                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               3282                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                4474777                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 82775                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         330016                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        5907886                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4422310                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             10330196                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1753064930                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             424170565                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          19118841                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    590955910                       # number of memory reference insts executed
system.cpu.iew.exec_branches                167475793                       # Number of branches executed
system.cpu.iew.exec_stores                  166785345                       # Number of stores executed
system.cpu.iew.exec_rate                     1.907911                       # Inst execution rate
system.cpu.iew.wb_sent                     1749812928                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1744955989                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1325071537                       # num instructions producing a value
system.cpu.iew.wb_consumers                1945900521                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.899086                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.680955                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       446680078                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           9936737                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    825484986                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.852231                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.435254                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    333347760     40.38%     40.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    193315332     23.42%     63.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     63291763      7.67%     71.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     92551196     11.21%     82.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     24974559      3.03%     85.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     27516320      3.33%     89.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      9293108      1.13%     90.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     11361813      1.38%     91.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     69833135      8.46%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    825484986                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262343                       # Number of memory references committed
system.cpu.commit.loads                     384102157                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758583                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              69833135                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   2731320630                       # The number of ROB reads
system.cpu.rob.rob_writes                  4012461124                       # The number of ROB writes
system.cpu.timesIdled                         3340699                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        32393108                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             826877109                       # Number of Instructions Simulated
system.cpu.cpi                               1.111217                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.111217                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.899914                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.899914                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2716389897                       # number of integer regfile reads
system.cpu.int_regfile_writes              1420532102                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      3421                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       19                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 597244921                       # number of cc regfile reads
system.cpu.cc_regfile_writes                405448259                       # number of cc regfile writes
system.cpu.misc_regfile_reads               964724023                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               697845146                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        1906044                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1906043                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      2330771                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq       136656                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp       136656                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       771758                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       771758                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       150484                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7672451                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           7822935                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       439424                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311357120                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      311796544                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         311796544                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus      8752064                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy     4906973310                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     215891495                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3953569925                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.cpu.icache.tags.replacements              5335                       # number of replacements
system.cpu.icache.tags.tagsinuse          1037.583647                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           161907582                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              6916                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          23410.581550                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1037.583647                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.506633                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.506633                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    161909622                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       161909622                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     161909622                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        161909622                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    161909622                       # number of overall hits
system.cpu.icache.overall_hits::total       161909622                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       145600                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        145600                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       145600                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         145600                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       145600                       # number of overall misses
system.cpu.icache.overall_misses::total        145600                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    941474740                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    941474740                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    941474740                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    941474740                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    941474740                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    941474740                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    162055222                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    162055222                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    162055222                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    162055222                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    162055222                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    162055222                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000898                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000898                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000898                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000898                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000898                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000898                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6466.172665                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  6466.172665                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  6466.172665                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  6466.172665                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  6466.172665                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  6466.172665                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          250                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          170                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 6                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    41.666667                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          170                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1982                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1982                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1982                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1982                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1982                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1982                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       143618                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       143618                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       143618                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       143618                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       143618                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       143618                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    562974254                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    562974254                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    562974254                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    562974254                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    562974254                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    562974254                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000886                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000886                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000886                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000886                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000886                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000886                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3919.942166                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3919.942166                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3919.942166                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  3919.942166                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3919.942166                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  3919.942166                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           352959                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29669.713018                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3697218                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           385325                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             9.595064                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     199249645000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21121.996968                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   224.213504                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8323.502546                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.644592                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.006842                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.254013                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.905448                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         3694                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1586802                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1590496                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2330771                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2330771                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1427                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1427                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       564889                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       564889                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         3694                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2151691                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2155385                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         3694                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2151691                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2155385                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3173                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       175624                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       178797                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data       135229                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       135229                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       206869                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       206869                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3173                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       382493                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        385666                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3173                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       382493                       # number of overall misses
system.cpu.l2cache.overall_misses::total       385666                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    242389500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  13196439955                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  13438829455                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      6577717                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total      6577717                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  15144418976                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  15144418976                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    242389500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  28340858931                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  28583248431                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    242389500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  28340858931                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  28583248431                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         6867                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1762426                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1769293                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2330771                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2330771                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       136656                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       136656                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       771758                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       771758                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         6867                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2534184                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2541051                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         6867                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2534184                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2541051                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.462065                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099649                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.101056                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.989558                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.989558                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268049                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.268049                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.462065                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.150933                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151774                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.462065                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.150933                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151774                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76391.270091                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75140.299475                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75162.499678                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    48.641320                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    48.641320                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73207.773886                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73207.773886                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76391.270091                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74095.104828                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74113.996129                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76391.270091                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74095.104828                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74113.996129                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       293572                       # number of writebacks
system.cpu.l2cache.writebacks::total           293572                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3173                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       175624                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       178797                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       135229                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       135229                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206869                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       206869                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3173                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       382493                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       385666                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3173                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       382493                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       385666                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    202707000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10956266955                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  11158973955                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   1356015260                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   1356015260                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12518797024                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12518797024                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    202707000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23475063979                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23677770979                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    202707000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23475063979                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23677770979                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.462065                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099649                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101056                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.989558                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.989558                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268049                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268049                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.462065                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150933                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151774                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.462065                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150933                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151774                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63884.966908                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62384.793394                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62411.416047                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10027.547789                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10027.547789                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60515.577607                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60515.577607                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63884.966908                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61373.839466                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61394.499331                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63884.966908                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61373.839466                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61394.499331                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           2530088                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4088.247279                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           395994774                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2534184                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            156.261256                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1794365000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4088.247279                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998107                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998107                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    247245006                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       247245006                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148235012                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148235012                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     395480018                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        395480018                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    395480018                       # number of overall hits
system.cpu.dcache.overall_hits::total       395480018                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2882280                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2882280                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       925190                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       925190                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3807470                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3807470                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3807470                       # number of overall misses
system.cpu.dcache.overall_misses::total       3807470                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  58083545125                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  58083545125                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  26852968678                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  26852968678                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  84936513803                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  84936513803                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  84936513803                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  84936513803                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    250127286                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    250127286                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    399287488                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    399287488                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    399287488                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    399287488                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011523                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011523                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006203                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006203                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009536                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009536                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009536                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009536                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20151.943991                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 20151.943991                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29024.274666                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 29024.274666                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22307.861599                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22307.861599                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22307.861599                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22307.861599                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         5821                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               669                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.701046                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2330771                       # number of writebacks
system.cpu.dcache.writebacks::total           2330771                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1119584                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1119584                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17046                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        17046                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1136630                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1136630                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1136630                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1136630                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762696                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1762696                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       908144                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       908144                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2670840                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2670840                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2670840                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2670840                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  30862153254                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  30862153254                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  24727931821                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  24727931821                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  55590085075                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  55590085075                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  55590085075                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  55590085075                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007047                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007047                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006088                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006088                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006689                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006689                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006689                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006689                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17508.494519                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17508.494519                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27229.086820                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27229.086820                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.708449                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.708449                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.708449                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.708449                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------