path: root/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.455304                       # Number of seconds simulated
sim_ticks                                455304035500                       # Number of ticks simulated
final_tick                               455304035500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  97470                       # Simulator instruction rate (inst/s)
host_op_rate                                   180233                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               53670129                       # Simulator tick rate (ticks/s)
host_mem_usage                                 427808                       # Number of bytes of host memory used
host_seconds                                  8483.38                       # Real time elapsed on the host
sim_insts                                   826877109                       # Number of instructions simulated
sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            225344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24524608                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24749952                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       225344                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          225344                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18812544                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18812544                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3521                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             383197                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                386718                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          293946                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               293946                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               494931                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             53864245                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                54359176                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          494931                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             494931                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          41318641                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               41318641                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          41318641                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              494931                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            53864245                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               95677817                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        386718                       # Number of read requests accepted
system.physmem.writeReqs                       293946                       # Number of write requests accepted
system.physmem.readBursts                      386718                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     293946                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24728064                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     21888                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18810880                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24749952                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18812544                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      342                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         191861                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24073                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26434                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24630                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24561                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23290                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23730                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24498                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24639                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23691                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23546                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24793                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24069                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23353                       # Per bank write bursts
system.physmem.perBankRdBursts::13              23015                       # Per bank write bursts
system.physmem.perBankRdBursts::14              24077                       # Per bank write bursts
system.physmem.perBankRdBursts::15              23977                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18554                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19855                       # Per bank write bursts
system.physmem.perBankWrBursts::2               18927                       # Per bank write bursts
system.physmem.perBankWrBursts::3               18928                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18036                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18437                       # Per bank write bursts
system.physmem.perBankWrBursts::6               18989                       # Per bank write bursts
system.physmem.perBankWrBursts::7               19175                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18571                       # Per bank write bursts
system.physmem.perBankWrBursts::9               17897                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18838                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17731                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17375                       # Per bank write bursts
system.physmem.perBankWrBursts::13              16985                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17811                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17811                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    455304010000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  386718                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 293946                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    381427                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4550                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       351                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        37                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6575                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    16890                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    17473                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    17565                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    17579                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17584                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17592                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    17616                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    17654                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    17597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    17680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    17600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    17664                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17861                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17545                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17481                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       147768                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      294.634833                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.118109                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     321.876505                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          54825     37.10%     37.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        40414     27.35%     64.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        13687      9.26%     73.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7337      4.97%     78.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         5611      3.80%     82.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         4054      2.74%     85.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         2966      2.01%     87.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2800      1.89%     89.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16074     10.88%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         147768                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17438                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        22.156612                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      209.316874                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          17424     99.92%     99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            9      0.05%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            3      0.02%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17438                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17438                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.855144                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.781564                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.520616                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           17233     98.82%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             149      0.85%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              26      0.15%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31              10      0.06%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               2      0.01%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               2      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               1      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               3      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67               1      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               2      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             2      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17438                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4282128000                       # Total ticks spent queuing
system.physmem.totMemAccLat               11526678000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1931880000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11082.80                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29832.80                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          54.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          41.31                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       54.36                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       41.32                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.75                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.42                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.32                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.49                       # Average write queue length when enqueuing
system.physmem.readRowHits                     317407                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    215108                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.15                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.18                       # Row buffer hit rate for writes
system.physmem.avgGap                       668911.55                       # Average gap between requests
system.physmem.pageHitRate                      78.27                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  571588920                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  311878875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1527575400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                977734800                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            29738046000                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            65814252570                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           215448936750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             314390013315                       # Total energy per rank (pJ)
system.physmem_0.averagePower              690.509916                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   357849000500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     15203500000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     82248835500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  545280120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  297523875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1485736200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                926555760                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            29738046000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            63167759955                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           217770421500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             313931323410                       # Total energy per rank (pJ)
system.physmem_1.averagePower              689.502473                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   361727973250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     15203500000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     78369769250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               231646337                       # Number of BP lookups
system.cpu.branchPred.condPredicted         231646337                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           9741961                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            132013407                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               129322217                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.961427                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                28025090                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1471468                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        910608093                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          186242841                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1278548490                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   231646337                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          157347307                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     713142960                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                20218451                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                       1278                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                97934                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        814720                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles         1319                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles           68                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 180536939                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2712428                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       5                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          910410345                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.611396                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.336099                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                499900768     54.91%     54.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 34011801      3.74%     58.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 33310917      3.66%     62.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 33621227      3.69%     66.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 27137981      2.98%     68.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 27875262      3.06%     72.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 37328628      4.10%     76.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 33745133      3.71%     79.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                183478628     20.15%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            910410345                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.254386                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.404060                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                127581888                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             450063290                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 239948731                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              82707211                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               10109225                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2232998831                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               10109225                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                159900312                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               230280409                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          34090                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 285603646                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             224482663                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2183077018                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                183617                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents              140318739                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               24297006                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               48974479                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2288425781                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5524582783                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3513207505                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             61088                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                674384927                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               2376                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           2343                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 427656429                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            530632285                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           210400238                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         240350662                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         72017394                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2112353898                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               24976                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1828941324                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            423887                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       578689030                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   1006760945                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          24424                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     910410345                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.008920                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.068672                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           325758066     35.78%     35.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           130835258     14.37%     50.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           120048462     13.19%     63.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           111501441     12.25%     75.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            91294731     10.03%     85.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            61344237      6.74%     92.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            43225981      4.75%     97.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            18968528      2.08%     99.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             7433641      0.82%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       910410345                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                11322546     42.44%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               12279843     46.03%     88.48% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3074079     11.52%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2717047      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1212867491     66.32%     66.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               388152      0.02%     66.49% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               3881000      0.21%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 102      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.70% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            435396374     23.81%     90.50% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           173691158      9.50%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1828941324                       # Type of FU issued
system.cpu.iq.rate                           2.008483                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    26676468                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014586                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4595362463                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2691335659                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1799336607                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               30885                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              66324                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         6516                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1852886556                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   14189                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        185525718                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    146532886                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       211598                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       388823                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     61240052                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        19518                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1112                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               10109225                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               169308479                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles              10486289                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2112378874                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            393422                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             530635043                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            210400238                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               7587                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                4508389                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3837371                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         388823                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        5739135                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4588886                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             10328021                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1807829650                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             429333816                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          21111674                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    599464610                       # number of memory reference insts executed
system.cpu.iew.exec_branches                171918385                       # Number of branches executed
system.cpu.iew.exec_stores                  170130794                       # Number of stores executed
system.cpu.iew.exec_rate                     1.985299                       # Inst execution rate
system.cpu.iew.wb_sent                     1804630771                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1799343123                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1369373146                       # num instructions producing a value
system.cpu.iew.wb_consumers                2092710816                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.975980                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.654354                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       583611522                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           9827684                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    831323520                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.839222                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.498579                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    362694832     43.63%     43.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    175144101     21.07%     64.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     57358727      6.90%     71.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     86263805     10.38%     81.97% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     27150861      3.27%     85.24% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     27127713      3.26%     88.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      9862872      1.19%     89.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      8848382      1.06%     90.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     76872227      9.25%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    831323520                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262343                       # Number of memory references committed
system.cpu.commit.loads                     384102157                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758583                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      1819099      0.12%      0.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        989721889     64.73%     64.85% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          306834      0.02%     64.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv          3878536      0.25%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       384102157     25.12%     90.24% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
system.cpu.commit.bw_lim_events              76872227                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   2867051516                       # The number of ROB reads
system.cpu.rob.rob_writes                  4304473794                       # The number of ROB writes
system.cpu.timesIdled                            2567                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          197748                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.101262                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.101262                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.908049                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.908049                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2763330538                       # number of integer regfile reads
system.cpu.int_regfile_writes              1467435539                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      6574                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      209                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 600926529                       # number of cc regfile reads
system.cpu.cc_regfile_writes                409661898                       # number of cc regfile writes
system.cpu.misc_regfile_reads               991625144                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2532368                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4088.654602                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           388337333                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2536464                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            153.101851                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1688557250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4088.654602                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998207                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998207                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          854                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3198                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         785792022                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        785792022                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    239684650                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       239684650                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148177346                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148177346                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     387861996                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        387861996                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    387861996                       # number of overall hits
system.cpu.dcache.overall_hits::total       387861996                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2782927                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2782927                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       982856                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       982856                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3765783                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3765783                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3765783                       # number of overall misses
system.cpu.dcache.overall_misses::total       3765783                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  59969889588                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  59969889588                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  31202214310                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  31202214310                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  91172103898                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  91172103898                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  91172103898                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  91172103898                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    242467577                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    242467577                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    391627779                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    391627779                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    391627779                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    391627779                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011478                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011478                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006589                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006589                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009616                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009616                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009616                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009616                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21549.214043                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21549.214043                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31746.475893                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31746.475893                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.663200                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24210.663200                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.663200                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24210.663200                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        10538                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            7                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1092                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               3                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.650183                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     2.333333                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2331685                       # number of writebacks
system.cpu.dcache.writebacks::total           2331685                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1017273                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1017273                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18365                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        18365                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1035638                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1035638                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1035638                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1035638                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1765654                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1765654                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       964491                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       964491                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2730145                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2730145                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2730145                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2730145                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32740632750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  32740632750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29421021688                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  29421021688                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62161654438                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  62161654438                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62161654438                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  62161654438                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007282                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007282                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006466                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006466                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006971                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006971                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006971                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006971                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18543.062656                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18543.062656                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30504.195154                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30504.195154                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22768.627468                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22768.627468                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22768.627468                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22768.627468                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements              6982                       # number of replacements
system.cpu.icache.tags.tagsinuse          1087.309225                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           180328938                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              8606                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          20953.862189                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1087.309225                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.530913                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.530913                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1624                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           10                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          309                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1182                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.792969                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         361276321                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        361276321                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    180331996                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       180331996                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     180331996                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        180331996                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    180331996                       # number of overall hits
system.cpu.icache.overall_hits::total       180331996                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       204942                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        204942                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       204942                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         204942                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       204942                       # number of overall misses
system.cpu.icache.overall_misses::total        204942                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1305386490                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1305386490                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1305386490                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1305386490                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1305386490                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1305386490                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    180536938                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    180536938                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    180536938                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    180536938                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    180536938                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    180536938                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001135                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.001135                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001135                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.001135                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001135                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.001135                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6369.541090                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  6369.541090                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  6369.541090                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  6369.541090                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  6369.541090                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  6369.541090                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1486                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                20                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    74.300000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2496                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2496                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2496                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2496                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2496                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2496                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       202446                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       202446                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       202446                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       202446                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       202446                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       202446                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    886113510                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    886113510                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    886113510                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    886113510                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    886113510                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    886113510                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001121                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001121                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001121                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.001121                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001121                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.001121                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4377.036395                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4377.036395                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4377.036395                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  4377.036395                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4377.036395                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  4377.036395                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           354037                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29694.655553                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3700890                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           386375                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             9.578492                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     197848612000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21120.417264                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   251.711772                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8322.526517                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.644544                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007682                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.253983                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.906209                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32338                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          224                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11738                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20294                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.986877                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         41723459                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        41723459                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst         5123                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1589228                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1594351                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2331685                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2331685                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1852                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1852                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       564007                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       564007                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         5123                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2153235                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2158358                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         5123                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2153235                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2158358                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3523                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       176215                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       179738                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data       191829                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       191829                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       207014                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       207014                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3523                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       383229                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        386752                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3523                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       383229                       # number of overall misses
system.cpu.l2cache.overall_misses::total       386752                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    289388750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  14251176250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  14540565000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     12592097                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     12592097                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16445422468                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16445422468                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    289388750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  30696598718                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  30985987468                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    289388750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  30696598718                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  30985987468                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         8646                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1765443                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1774089                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2331685                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2331685                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       193681                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       193681                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       771021                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       771021                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         8646                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2536464                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2545110                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         8646                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2536464                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2545110                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.407472                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.099813                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.101313                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990438                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990438                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268493                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.268493                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.407472                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.151088                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151959                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.407472                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.151088                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151959                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82142.705081                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80873.797634                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80898.669174                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    65.642301                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    65.642301                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79441.112524                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79441.112524                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82142.705081                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80099.884711                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80118.493164                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82142.705081                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80099.884711                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80118.493164                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       293946                       # number of writebacks
system.cpu.l2cache.writebacks::total           293946                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total            1                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3522                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       176215                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       179737                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       191829                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       191829                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       207014                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       207014                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3522                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       383229                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       386751                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3522                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       383229                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       386751                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    245309750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  12046131750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  12291441500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3462043228                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3462043228                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  13856748032                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  13856748032                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    245309750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  25902879782                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  26148189532                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    245309750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  25902879782                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  26148189532                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.407356                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.099813                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.101312                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990438                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990438                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268493                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268493                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.407356                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151088                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151958                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.407356                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151088                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151958                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69650.695627                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68360.421928                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68385.705225                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18047.548744                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18047.548744                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66936.284657                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66936.284657                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69650.695627                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67591.126407                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.882152                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69650.695627                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67591.126407                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.882152                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        1967889                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1967888                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      2331685                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq       193681                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp       193681                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       771021                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       771021                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       211091                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7791975                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8003066                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       553280                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311561536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          312114816                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      193800                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      5264276                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            5264276    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5264276                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4991831371                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     304197990                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3984504311                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.membus.trans_dist::ReadReq              179736                       # Transaction distribution
system.membus.trans_dist::ReadResp             179736                       # Transaction distribution
system.membus.trans_dist::Writeback            293946                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           191861                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          191861                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206982                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206982                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1451104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1451104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1451104                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43562496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43562496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                43562496                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            872525                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  872525    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              872525                       # Request fanout histogram
system.membus.reqLayer0.occupancy          2241314053                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2430435187                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)

---------- End Simulation Statistics   ----------