path: root/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.403427                       # Number of seconds simulated
sim_ticks                                403427114500                       # Number of ticks simulated
final_tick                               403427114500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  97075                       # Simulator instruction rate (inst/s)
host_op_rate                                   179503                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               47362243                       # Simulator tick rate (ticks/s)
host_mem_usage                                 432836                       # Number of bytes of host memory used
host_seconds                                  8517.91                       # Real time elapsed on the host
sim_insts                                   826877109                       # Number of instructions simulated
sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            163328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24540032                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24703360                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       163328                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          163328                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18887104                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18887104                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2552                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             383438                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                385990                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          295111                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               295111                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               404851                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             60828911                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                61233762                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          404851                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             404851                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          46816645                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               46816645                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          46816645                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              404851                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            60828911                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              108050407                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        385990                       # Number of read requests accepted
system.physmem.writeReqs                       295111                       # Number of write requests accepted
system.physmem.readBursts                      385990                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     295111                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24683712                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     19648                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18885056                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24703360                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18887104                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      307                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24081                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26417                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24826                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24490                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23233                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23715                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24493                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24296                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23625                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23520                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24786                       # Per bank write bursts
system.physmem.perBankRdBursts::11              23961                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23329                       # Per bank write bursts
system.physmem.perBankRdBursts::13              22937                       # Per bank write bursts
system.physmem.perBankRdBursts::14              24074                       # Per bank write bursts
system.physmem.perBankRdBursts::15              23900                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18616                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19936                       # Per bank write bursts
system.physmem.perBankWrBursts::2               19195                       # Per bank write bursts
system.physmem.perBankWrBursts::3               19026                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18116                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18513                       # Per bank write bursts
system.physmem.perBankWrBursts::6               19137                       # Per bank write bursts
system.physmem.perBankWrBursts::7               19093                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18645                       # Per bank write bursts
system.physmem.perBankWrBursts::9               17955                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18907                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17752                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17408                       # Per bank write bursts
system.physmem.perBankWrBursts::13              17006                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17895                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17879                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    403427072500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  385990                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 295111                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    380786                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4546                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       308                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6569                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    16986                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    17529                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    17639                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    17648                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17662                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17655                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17706                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    17661                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    17722                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    17690                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    17764                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    17770                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    17759                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17891                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17597                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17537                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       39                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       146923                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      296.528440                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     175.268112                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     322.869611                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          54238     36.92%     36.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        39906     27.16%     64.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        13861      9.43%     73.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7527      5.12%     78.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         5392      3.67%     82.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         3977      2.71%     85.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         3022      2.06%     87.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2802      1.91%     88.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16198     11.02%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         146923                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17507                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        22.029360                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      217.887118                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          17497     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            3      0.02%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17507                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17507                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.854915                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.776896                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.816664                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           17316     98.91%     98.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             131      0.75%     99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              34      0.19%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31               8      0.05%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               2      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               3      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               1      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71               1      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             2      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17507                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4287997000                       # Total ticks spent queuing
system.physmem.totMemAccLat               11519553250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1928415000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11117.93                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29867.93                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          61.19                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          46.81                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       61.23                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       46.82                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.84                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.48                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.37                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.97                       # Average write queue length when enqueuing
system.physmem.readRowHits                     318108                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    215717                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.48                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.10                       # Row buffer hit rate for writes
system.physmem.avgGap                       592316.08                       # Average gap between requests
system.physmem.pageHitRate                      78.41                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  568655640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  310278375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1525157400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                982374480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            26349510720                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            62248054410                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           187449302250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             279433333275                       # Total energy per rank (pJ)
system.physmem_0.averagePower              692.658624                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   311288113000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     13471120000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     78663487000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  541689120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  295564500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1482585000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                929322720                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            26349510720                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            60147053505                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           189292285500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             279038011065                       # Total energy per rank (pJ)
system.physmem_1.averagePower              691.678700                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   314369366250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     13471120000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     75582067750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               219277494                       # Number of BP lookups
system.cpu.branchPred.condPredicted         219277494                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           8530091                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            124020025                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               121811454                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             98.219182                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                27064699                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1406143                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        806854230                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          175890438                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1208681477                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   219277494                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          148876153                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     621110348                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                17764353                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        230                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                91101                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        722324                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles         1300                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles           17                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 170768195                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2322348                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       3                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          806697934                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.787860                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.367990                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                416692027     51.65%     51.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 32514924      4.03%     55.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 31852485      3.95%     59.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 32737208      4.06%     63.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 26535487      3.29%     66.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 26940530      3.34%     70.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 35175393      4.36%     74.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 31366288      3.89%     78.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                172883592     21.43%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            806697934                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.271768                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.498017                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                120436174                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             370050155                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 225346926                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              81982503                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                8882176                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2132175908                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                8882176                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                152549485                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               150499256                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          41235                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 271495233                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             223230549                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2088541699                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                133771                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents              138231059                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               24777266                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               50120464                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2190713921                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5278163786                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3357090809                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             59859                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                576673067                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               3285                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           3078                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 422612041                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            507148674                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           200824572                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         228968697                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         68242516                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2023165492                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               27791                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1789027795                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            414599                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       494204582                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    832990276                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          27239                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     806697934                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.217717                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.070743                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           238149356     29.52%     29.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           123576451     15.32%     44.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           118711028     14.72%     59.56% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           107747587     13.36%     72.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            89829016     11.14%     84.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            60156883      7.46%     91.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            42289548      5.24%     96.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            18955760      2.35%     99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             7282305      0.90%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       806697934                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                11505863     42.68%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               12343295     45.78%     88.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3110421     11.54%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2715990      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1183116627     66.13%     66.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               369664      0.02%     66.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               3881147      0.22%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 118      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 58      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                 380      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            428537576     23.95%     90.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           170406235      9.53%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1789027795                       # Type of FU issued
system.cpu.iq.rate                           2.217287                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    26959579                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.015069                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4412098039                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2517646847                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1762392188                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               29663                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              69110                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         5652                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1813258358                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   13026                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        185949248                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    123048931                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       213773                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       371791                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     51664386                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        23126                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1127                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                8882176                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                97661574                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               6126306                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2023193283                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            371095                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             507151088                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            200824572                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              12039                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1828108                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3395741                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         371791                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4845230                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4136012                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8981242                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1770011750                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             423132476                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          19016045                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    590347878                       # number of memory reference insts executed
system.cpu.iew.exec_branches                168976982                       # Number of branches executed
system.cpu.iew.exec_stores                  167215402                       # Number of stores executed
system.cpu.iew.exec_rate                     2.193719                       # Inst execution rate
system.cpu.iew.wb_sent                     1766881473                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1762397840                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1339889750                       # num instructions producing a value
system.cpu.iew.wb_consumers                2050179516                       # num instructions consuming a value
system.cpu.iew.wb_rate                       2.184283                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.653548                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts       494265381                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           8610728                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    739482483                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.067647                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.576172                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    275479046     37.25%     37.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    172073402     23.27%     60.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     55823940      7.55%     68.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     86367064     11.68%     79.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     25894199      3.50%     83.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     26482728      3.58%     86.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      9848964      1.33%     88.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      9023113      1.22%     89.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     78490027     10.61%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    739482483                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262343                       # Number of memory references committed
system.cpu.commit.loads                     384102157                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758583                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      1819099      0.12%      0.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        989721889     64.73%     64.85% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          306834      0.02%     64.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv          3878536      0.25%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       384102157     25.12%     90.24% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
system.cpu.commit.bw_lim_events              78490027                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   2684246538                       # The number of ROB reads
system.cpu.rob.rob_writes                  4113897788                       # The number of ROB writes
system.cpu.timesIdled                            1953                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          156296                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.975785                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.975785                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.024816                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.024816                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2722631435                       # number of integer regfile reads
system.cpu.int_regfile_writes              1435841734                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      5845                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      533                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 596631944                       # number of cc regfile reads
system.cpu.cc_regfile_writes                405465564                       # number of cc regfile writes
system.cpu.misc_regfile_reads               971632310                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2530979                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4087.807694                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           381987598                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2535075                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            150.680985                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1673396500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4087.807694                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998000                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998000                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           28                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          866                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3174                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         773071261                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        773071261                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    233342532                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       233342532                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148176085                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148176085                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     381518617                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        381518617                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    381518617                       # number of overall hits
system.cpu.dcache.overall_hits::total       381518617                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2765359                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2765359                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       984117                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       984117                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3749476                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3749476                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3749476                       # number of overall misses
system.cpu.dcache.overall_misses::total       3749476                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  58561335000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  58561335000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  30709347495                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  30709347495                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  89270682495                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  89270682495                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  89270682495                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  89270682495                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    236107891                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    236107891                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    385268093                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    385268093                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    385268093                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    385268093                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011712                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011712                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006598                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006598                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009732                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009732                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009732                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009732                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21176.756797                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21176.756797                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31204.976131                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31204.976131                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.842221                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23808.842221                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.842221                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23808.842221                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         9995                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets           16                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1075                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.297674                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets            8                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2330614                       # number of writebacks
system.cpu.dcache.writebacks::total           2330614                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1000418                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1000418                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19400                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        19400                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1019818                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1019818                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1019818                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1019818                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764941                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1764941                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       964717                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       964717                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2729658                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2729658                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2729658                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2729658                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33563285500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  33563285500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29489872497                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  29489872497                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63053157997                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  63053157997                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63053157997                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  63053157997                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007475                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007475                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006468                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006468                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007085                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.007085                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007085                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.007085                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19016.661463                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19016.661463                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30568.417989                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30568.417989                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23099.288628                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23099.288628                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23099.288628                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23099.288628                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements              6598                       # number of replacements
system.cpu.icache.tags.tagsinuse          1037.931814                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           170560002                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              8206                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          20784.791860                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1037.931814                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.506803                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.506803                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1608                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           48                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          316                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1161                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.785156                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         341739287                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        341739287                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    170563080                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       170563080                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     170563080                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        170563080                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    170563080                       # number of overall hits
system.cpu.icache.overall_hits::total       170563080                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       205114                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        205114                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       205114                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         205114                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       205114                       # number of overall misses
system.cpu.icache.overall_misses::total        205114                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1195791500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1195791500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1195791500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1195791500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1195791500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1195791500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    170768194                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    170768194                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    170768194                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    170768194                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    170768194                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    170768194                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001201                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.001201                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001201                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.001201                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001201                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.001201                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  5829.887282                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  5829.887282                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  5829.887282                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  5829.887282                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  5829.887282                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  5829.887282                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          766                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                10                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    76.600000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks         6598                       # number of writebacks
system.cpu.icache.writebacks::total              6598                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2213                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2213                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2213                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2213                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2213                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2213                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       202901                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       202901                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       202901                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       202901                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       202901                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       202901                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    903987500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    903987500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    903987500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    903987500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    903987500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    903987500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001188                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001188                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001188                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.001188                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001188                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.001188                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4455.313182                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4455.313182                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4455.313182                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  4455.313182                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4455.313182                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  4455.313182                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           355236                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29620.195049                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3892684                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           387566                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            10.043925                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     189331361500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 21023.013022                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   186.931576                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8410.250450                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.641571                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005705                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.256660                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.903937                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32330                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          225                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13404                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18615                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.986633                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43275096                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43275096                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks      2330614                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      2330614                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks         6188                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total         6188                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1825                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1825                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       563621                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       563621                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5638                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         5638                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1587969                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1587969                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         5638                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2151590                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2157228                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         5638                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2151590                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2157228                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data       192758                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       192758                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       206906                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       206906                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2554                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2554                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176579                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       176579                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2554                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       383485                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        386039                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2554                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       383485                       # number of overall misses
system.cpu.l2cache.overall_misses::total       386039                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     12752500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     12752500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16413935500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16413935500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    209752500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    209752500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14193739500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  14193739500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    209752500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  30607675000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  30817427500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    209752500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  30607675000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  30817427500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks      2330614                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      2330614                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks         6188                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total         6188                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       194583                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       194583                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       770527                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       770527                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8192                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         8192                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1764548                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1764548                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         8192                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2535075                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2543267                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         8192                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2535075                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2543267                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990621                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990621                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268525                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.268525                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.311768                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.311768                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.100070                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.100070                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.311768                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.151272                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151789                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.311768                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.151272                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151789                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    66.158084                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    66.158084                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79330.398828                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79330.398828                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82127.055599                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82127.055599                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80381.809275                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80381.809275                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82127.055599                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79814.529903                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79829.829370                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82127.055599                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79814.529903                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79829.829370                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       295111                       # number of writebacks
system.cpu.l2cache.writebacks::total           295111                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            7                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            7                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       192758                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       192758                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206906                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       206906                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2553                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2553                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176579                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176579                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2553                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       383485                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       386038                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2553                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       383485                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       386038                       # number of overall MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3718916993                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3718916993                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14344875500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14344875500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    184165500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    184165500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12427929541                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12427929541                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    184165500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26772805041                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  26956970541                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    184165500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26772805041                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  26956970541                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990621                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990621                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268525                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268525                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.311646                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.311646                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.100070                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.100070                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.311646                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151272                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151788                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.311646                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151272                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151788                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19293.191427                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19293.191427                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69330.398828                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69330.398828                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72136.897767                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72136.897767                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70381.696244                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70381.696244                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72136.897767                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.477857                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69829.836806                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72136.897767                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.477857                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69829.836806                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5470136                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2729158                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests       209637                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         3579                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3579                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp       1967447                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      2625725                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean         6598                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       260490                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq       194583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp       194583                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       770527                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       770527                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       202901                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1764548                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       217689                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7990295                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8207984                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       946432                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311404096                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          312350528                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      549945                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      3287795                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.123088                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.328538                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2883107     87.69%     87.69% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             404688     12.31%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        3287795                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5100517412                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     304355486                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3899906073                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             179130                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       295111                       # Transaction distribution
system.membus.trans_dist::CleanEvict            56614                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           192805                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206859                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206859                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        179131                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1316509                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1316509                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1316509                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43590400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43590400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                43590400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            930520                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  930520    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              930520                       # Request fanout histogram
system.membus.reqLayer0.occupancy          2239434504                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2041939000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)

---------- End Simulation Statistics   ----------