path: root/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.417251                       # Number of seconds simulated
sim_ticks                                417250627500                       # Number of ticks simulated
final_tick                               417250627500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  80283                       # Simulator instruction rate (inst/s)
host_op_rate                                   148451                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               40511385                       # Simulator tick rate (ticks/s)
host_mem_usage                                 420456                       # Number of bytes of host memory used
host_seconds                                 10299.59                       # Real time elapsed on the host
sim_insts                                   826877109                       # Number of instructions simulated
sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            222336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24526912                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24749248                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       222336                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          222336                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18882944                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18882944                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3474                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             383233                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                386707                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          295046                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               295046                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               532860                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             58782205                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                59315065                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          532860                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             532860                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          45255640                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               45255640                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          45255640                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              532860                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            58782205                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              104570704                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        386709                       # Number of read requests accepted
system.physmem.writeReqs                       295046                       # Number of write requests accepted
system.physmem.readBursts                      386709                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     295046                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24728384                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     20992                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18881536                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24749376                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18882944                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      328                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         188175                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24066                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26415                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24733                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24594                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23512                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23778                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24541                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24366                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23719                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23940                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24780                       # Per bank write bursts
system.physmem.perBankRdBursts::11              24034                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23243                       # Per bank write bursts
system.physmem.perBankRdBursts::13              22939                       # Per bank write bursts
system.physmem.perBankRdBursts::14              23855                       # Per bank write bursts
system.physmem.perBankRdBursts::15              23866                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18622                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19926                       # Per bank write bursts
system.physmem.perBankWrBursts::2               18981                       # Per bank write bursts
system.physmem.perBankWrBursts::3               19010                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18166                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18514                       # Per bank write bursts
system.physmem.perBankWrBursts::6               19130                       # Per bank write bursts
system.physmem.perBankWrBursts::7               19080                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18668                       # Per bank write bursts
system.physmem.perBankWrBursts::9               18206                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18899                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17761                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17398                       # Per bank write bursts
system.physmem.perBankWrBursts::13              16998                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17806                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17859                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    417250612500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  386709                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 295046                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    381319                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4687                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       326                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        40                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6559                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    16925                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    17530                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    17602                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    17649                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17658                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17667                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17730                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    17675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    17721                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    17676                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    17739                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    17735                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    17731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17918                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17539                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       23                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       11                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       147516                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      295.624068                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.465729                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     322.989289                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          54788     37.14%     37.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        40113     27.19%     64.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        13739      9.31%     73.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7486      5.07%     78.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         5440      3.69%     82.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         3806      2.58%     84.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         3042      2.06%     87.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2827      1.92%     88.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16275     11.03%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         147516                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17514                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        22.060866                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      217.469599                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          17503     99.94%     99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            6      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            2      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17514                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17514                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.845038                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.773915                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.557012                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           17326     98.93%     98.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             134      0.77%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              31      0.18%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31               5      0.03%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               2      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               2      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               1      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               1      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67               1      0.01%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79               3      0.02%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::212-215             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17514                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4299952250                       # Total ticks spent queuing
system.physmem.totMemAccLat               11544596000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1931905000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11128.79                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29878.79                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          59.27                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          45.25                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       59.32                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       45.26                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.82                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.35                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.85                       # Average write queue length when enqueuing
system.physmem.readRowHits                     317964                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    215920                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.29                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.18                       # Row buffer hit rate for writes
system.physmem.avgGap                       612024.28                       # Average gap between requests
system.physmem.pageHitRate                      78.35                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  570008880                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  311016750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1528831200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                981214560                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            27252713280                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            63403052535                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           194733182250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             288780019455                       # Total energy per rank (pJ)
system.physmem_0.averagePower              692.103393                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   323396501250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     13932880000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     79920713750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  545189400                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  297474375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1484854800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                930437280                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            27252713280                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            61562082780                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           196348068000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             288420819915                       # Total energy per rank (pJ)
system.physmem_1.averagePower              691.242519                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   326101005500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     13932880000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     77215953250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               230048146                       # Number of BP lookups
system.cpu.branchPred.condPredicted         230048146                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           9737361                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            131481620                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               128745848                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             97.919274                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                27747759                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1468593                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        834501256                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          185122313                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1269330935                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   230048146                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          156493607                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     638172933                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                20204179                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        520                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                97554                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        807935                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles         1425                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles           52                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 179438196                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2717621                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       7                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          834304821                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.829912                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.382398                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                426682795     51.14%     51.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 33772943      4.05%     55.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 32839651      3.94%     59.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 33391032      4.00%     63.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 27218620      3.26%     66.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 27672975      3.32%     69.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 36987549      4.43%     74.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 33695145      4.04%     78.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                182044111     21.82%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            834304821                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.275671                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.521065                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                127569243                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             374855550                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 240395072                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              81382867                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               10102089                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2225227906                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles               10102089                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                159580734                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               159860016                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          39443                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 285688559                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             219033980                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2175097177                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                169662                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents              136298138                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               24249327                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               48475339                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2279313761                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5500897024                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3499022597                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             55311                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                665272907                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               3132                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           2892                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 414765306                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            528353068                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           209871702                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         239280350                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         72161896                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2101070031                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               24820                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1826918488                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            398350                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       572106150                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    973941611                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          24268                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     834304821                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.189749                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.072611                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           254655960     30.52%     30.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           125511852     15.04%     45.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           119464444     14.32%     59.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           111099885     13.32%     73.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            92302861     11.06%     84.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            61631743      7.39%     91.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            43068652      5.16%     96.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            19159370      2.30%     99.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             7410054      0.89%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       834304821                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                11329083     42.46%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.46% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               12292434     46.07%     88.53% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3060904     11.47%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2718358      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1211226700     66.30%     66.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               389616      0.02%     66.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               3881120      0.21%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 131      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   2      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 24      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                 414      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            434992081     23.81%     90.49% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           173710042      9.51%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1826918488                       # Type of FU issued
system.cpu.iq.rate                           2.189234                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    26682421                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.014605                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4515190603                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2673460892                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1796856978                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               31965                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              70764                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         6893                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1850867797                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   14754                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        185700457                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    144253147                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       213808                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       384332                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     60711516                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        18958                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           979                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               10102089                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles               107041835                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               6156081                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2101094851                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            396815                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             528355304                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            209871702                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               6976                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1865462                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3396504                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         384332                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        5739761                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4560590                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             10300351                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1805510192                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             428784370                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          21408296                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    598976056                       # number of memory reference insts executed
system.cpu.iew.exec_branches                171763411                       # Number of branches executed
system.cpu.iew.exec_stores                  170191686                       # Number of stores executed
system.cpu.iew.exec_rate                     2.163580                       # Inst execution rate
system.cpu.iew.wb_sent                     1802107285                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1796863871                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1368034303                       # num instructions producing a value
system.cpu.iew.wb_consumers                2090148534                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.153219                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.654515                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       572186286                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           9823371                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    756648341                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.020739                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.547802                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    287852257     38.04%     38.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    175420323     23.18%     61.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     57242279      7.57%     68.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     86327184     11.41%     80.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     27107734      3.58%     83.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     27120897      3.58%     87.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      9790292      1.29%     88.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      8973905      1.19%     89.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     76813470     10.15%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    756648341                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262343                       # Number of memory references committed
system.cpu.commit.loads                     384102157                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758583                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      1819099      0.12%      0.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        989721889     64.73%     64.85% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          306834      0.02%     64.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv          3878536      0.25%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       384102157     25.12%     90.24% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
system.cpu.commit.bw_lim_events              76813470                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   2781009858                       # The number of ROB reads
system.cpu.rob.rob_writes                  4280193893                       # The number of ROB writes
system.cpu.timesIdled                            2297                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          196435                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.009220                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.009220                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.990864                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.990864                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2761953724                       # number of integer regfile reads
system.cpu.int_regfile_writes              1465013469                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      7172                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      467                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 600919347                       # number of cc regfile reads
system.cpu.cc_regfile_writes                409646269                       # number of cc regfile writes
system.cpu.misc_regfile_reads               990116456                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2534268                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4088.021372                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           387614743                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2538364                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            152.702584                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1679458500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4088.021372                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998052                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998052                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           26                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           28                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          878                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3164                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         784355902                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        784355902                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    238963393                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       238963393                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148180513                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148180513                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     387143906                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        387143906                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    387143906                       # number of overall hits
system.cpu.dcache.overall_hits::total       387143906                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2785174                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2785174                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       979689                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       979689                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3764863                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3764863                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3764863                       # number of overall misses
system.cpu.dcache.overall_misses::total       3764863                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  59469395500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  59469395500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  30831236499                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  30831236499                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  90300631999                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  90300631999                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  90300631999                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  90300631999                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    241748567                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    241748567                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    390908769                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    390908769                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    390908769                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    390908769                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011521                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011521                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006568                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006568                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009631                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009631                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009631                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009631                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21352.129346                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21352.129346                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31470.432453                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31470.432453                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23985.104371                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23985.104371                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23985.104371                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23985.104371                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        10830                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets           28                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1133                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.558694                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets            7                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2332705                       # number of writebacks
system.cpu.dcache.writebacks::total           2332705                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1017213                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1017213                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19267                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        19267                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1036480                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1036480                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1036480                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1036480                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1767961                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1767961                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       960422                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       960422                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2728383                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2728383                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2728383                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2728383                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33609753000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  33609753000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  29619647000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  29619647000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63229400000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  63229400000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63229400000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  63229400000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007313                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007313                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006439                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006439                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006980                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006980                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006980                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006980                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.460638                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.460638                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30840.242102                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30840.242102                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23174.678922                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23174.678922                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23174.678922                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23174.678922                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements              6976                       # number of replacements
system.cpu.icache.tags.tagsinuse          1050.495149                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           179233953                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              8576                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          20899.481460                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1050.495149                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.512937                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.512937                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1600                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           46                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          313                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1156                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.781250                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         359075141                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        359075141                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    179236865                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       179236865                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     179236865                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        179236865                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    179236865                       # number of overall hits
system.cpu.icache.overall_hits::total       179236865                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       201330                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        201330                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       201330                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         201330                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       201330                       # number of overall misses
system.cpu.icache.overall_misses::total        201330                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1280282499                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1280282499                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1280282499                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1280282499                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1280282499                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1280282499                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    179438195                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    179438195                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    179438195                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    179438195                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    179438195                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    179438195                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001122                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.001122                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001122                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.001122                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001122                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.001122                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6359.124318                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  6359.124318                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  6359.124318                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  6359.124318                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  6359.124318                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  6359.124318                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          947                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           40                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    63.133333                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           40                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2576                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2576                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2576                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2576                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2576                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2576                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       198754                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       198754                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       198754                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       198754                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       198754                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       198754                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    967804499                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    967804499                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    967804499                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    967804499                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    967804499                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    967804499                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001108                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001108                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001108                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.001108                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001108                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.001108                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4869.358599                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4869.358599                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4869.358599                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  4869.358599                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4869.358599                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  4869.358599                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           354031                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29616.745203                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3899360                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           386379                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            10.092060                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     197715227000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 20955.071178                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   251.225127                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8410.448899                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.639498                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007667                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.256667                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.903831                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32348                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1            6                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          240                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13348                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18673                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987183                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43294513                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43294513                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      2332705                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2332705                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1885                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1885                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       564153                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       564153                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5133                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         5133                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590938                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1590938                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         5133                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2155091                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2160224                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         5133                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2155091                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2160224                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data       188135                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       188135                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       206662                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       206662                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3478                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         3478                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176611                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       176611                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3478                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       383273                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        386751                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3478                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       383273                       # number of overall misses
system.cpu.l2cache.overall_misses::total       386751                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13341000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     13341000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16380998500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16380998500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    281189000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    281189000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14213384500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  14213384500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    281189000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  30594383000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  30875572000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    281189000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  30594383000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  30875572000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      2332705                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2332705                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       190020                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       190020                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       770815                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       770815                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8611                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         8611                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1767549                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1767549                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         8611                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2538364                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2546975                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         8611                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2538364                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2546975                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990080                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990080                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268108                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.268108                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.403902                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.403902                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099919                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099919                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.403902                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.150992                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151847                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.403902                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.150992                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151847                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    70.911845                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    70.911845                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79264.685815                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79264.685815                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80847.901093                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80847.901093                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80478.478124                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80478.478124                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80847.901093                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79823.997516                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79833.205344                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80847.901093                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79823.997516                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79833.205344                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       295046                       # number of writebacks
system.cpu.l2cache.writebacks::total           295046                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            1                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         2001                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         2001                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       188135                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       188135                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206662                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       206662                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3477                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3477                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176611                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176611                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3477                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       383273                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       386750                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3477                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       383273                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       386750                       # number of overall MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3958974717                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3958974717                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14314378500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14314378500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    246372000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    246372000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12447274500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12447274500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    246372000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26761653000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  27008025000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    246372000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26761653000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  27008025000                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990080                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990080                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268108                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268108                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.403786                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.403786                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099919                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099919                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.403786                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150992                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151847                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.403786                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150992                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151847                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21043.265299                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21043.265299                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69264.685815                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69264.685815                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70857.635893                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70857.635893                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70478.478124                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70478.478124                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70857.635893                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69823.997516                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69833.290239                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70857.635893                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69823.997516                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69833.290239                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp       1966300                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      2627751                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       256160                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq       190020                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp       190020                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       770815                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       770815                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       198754                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1767549                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       213879                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7980131                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8194010                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       550912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311748416                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          312299328                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      544174                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      5822413                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.060805                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.238972                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            5468382     93.92%     93.92% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             354031      6.08%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5822413                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5094765649                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     298130492                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3902557066                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             180085                       # Transaction distribution
system.membus.trans_dist::Writeback            295046                       # Transaction distribution
system.membus.trans_dist::CleanEvict            57422                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           188175                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          188175                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206622                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206622                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        180087                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1502234                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1502234                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1502234                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43632192                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43632192                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                43632192                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            927352                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  927352    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              927352                       # Request fanout histogram
system.membus.reqLayer0.occupancy          2233095783                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2421970141                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)

---------- End Simulation Statistics   ----------