path: root/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.403931                       # Number of seconds simulated
sim_ticks                                403931323500                       # Number of ticks simulated
final_tick                               403931323500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  95186                       # Simulator instruction rate (inst/s)
host_op_rate                                   176009                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               46498470                       # Simulator tick rate (ticks/s)
host_mem_usage                                 433064                       # Number of bytes of host memory used
host_seconds                                  8686.98                       # Real time elapsed on the host
sim_insts                                   826877109                       # Number of instructions simulated
sim_ops                                    1528988701                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            217984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          24500544                       # Number of bytes read from this memory
system.physmem.bytes_read::total             24718528                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       217984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          217984                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     18869632                       # Number of bytes written to this memory
system.physmem.bytes_written::total          18869632                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3406                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             382821                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                386227                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          294838                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               294838                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               539656                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             60655222                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                61194878                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          539656                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             539656                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          46714951                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               46714951                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          46714951                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              539656                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            60655222                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              107909829                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        386228                       # Number of read requests accepted
system.physmem.writeReqs                       294838                       # Number of write requests accepted
system.physmem.readBursts                      386228                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                     294838                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 24699456                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     19136                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  18868032                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  24718592                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               18869632                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      299                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs         196128                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               24062                       # Per bank write bursts
system.physmem.perBankRdBursts::1               26430                       # Per bank write bursts
system.physmem.perBankRdBursts::2               24903                       # Per bank write bursts
system.physmem.perBankRdBursts::3               24577                       # Per bank write bursts
system.physmem.perBankRdBursts::4               23181                       # Per bank write bursts
system.physmem.perBankRdBursts::5               23704                       # Per bank write bursts
system.physmem.perBankRdBursts::6               24550                       # Per bank write bursts
system.physmem.perBankRdBursts::7               24303                       # Per bank write bursts
system.physmem.perBankRdBursts::8               23663                       # Per bank write bursts
system.physmem.perBankRdBursts::9               23568                       # Per bank write bursts
system.physmem.perBankRdBursts::10              24789                       # Per bank write bursts
system.physmem.perBankRdBursts::11              23975                       # Per bank write bursts
system.physmem.perBankRdBursts::12              23330                       # Per bank write bursts
system.physmem.perBankRdBursts::13              22932                       # Per bank write bursts
system.physmem.perBankRdBursts::14              24089                       # Per bank write bursts
system.physmem.perBankRdBursts::15              23873                       # Per bank write bursts
system.physmem.perBankWrBursts::0               18604                       # Per bank write bursts
system.physmem.perBankWrBursts::1               19922                       # Per bank write bursts
system.physmem.perBankWrBursts::2               19191                       # Per bank write bursts
system.physmem.perBankWrBursts::3               18985                       # Per bank write bursts
system.physmem.perBankWrBursts::4               18090                       # Per bank write bursts
system.physmem.perBankWrBursts::5               18485                       # Per bank write bursts
system.physmem.perBankWrBursts::6               19138                       # Per bank write bursts
system.physmem.perBankWrBursts::7               19082                       # Per bank write bursts
system.physmem.perBankWrBursts::8               18642                       # Per bank write bursts
system.physmem.perBankWrBursts::9               17946                       # Per bank write bursts
system.physmem.perBankWrBursts::10              18887                       # Per bank write bursts
system.physmem.perBankWrBursts::11              17737                       # Per bank write bursts
system.physmem.perBankWrBursts::12              17398                       # Per bank write bursts
system.physmem.perBankWrBursts::13              16988                       # Per bank write bursts
system.physmem.perBankWrBursts::14              17875                       # Per bank write bursts
system.physmem.perBankWrBursts::15              17843                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    403931308500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  386228                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                 294838                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    380968                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      4611                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       308                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        33                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     6145                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     6562                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    16953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    17544                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    17606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    17653                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    17643                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    17627                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    17674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    17646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    17722                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    17675                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    17751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    17740                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    17710                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    17865                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    17590                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    17529                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       27                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       14                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        7                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       146866                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      296.637860                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     175.325639                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     323.046473                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          54140     36.86%     36.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        39981     27.22%     64.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        13765      9.37%     73.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         7667      5.22%     78.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         5371      3.66%     82.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         3914      2.67%     85.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         3025      2.06%     87.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         2731      1.86%     88.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        16272     11.08%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         146866                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         17494                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        22.060078                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      218.173610                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          17485     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            4      0.02%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            3      0.02%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           17494                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         17494                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.852235                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.776145                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.682764                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           17296     98.87%     98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             143      0.82%     99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              28      0.16%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31               5      0.03%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35               3      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39               3      0.02%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43               1      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47               1      0.01%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55               1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59               1      0.01%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63               2      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67               3      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               1      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111             1      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-219             1      0.01%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           17494                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4291077750                       # Total ticks spent queuing
system.physmem.totMemAccLat               11527246500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1929645000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11118.83                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29868.83                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          61.15                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          46.71                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       61.20                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       46.71                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.84                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.48                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.35                       # Average write queue length when enqueuing
system.physmem.readRowHits                     317989                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    215873                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.40                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.22                       # Row buffer hit rate for writes
system.physmem.avgGap                       593086.88                       # Average gap between requests
system.physmem.pageHitRate                      78.42                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  567438480                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  309614250                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1526405400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                981499680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            26382567120                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            62258546970                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           187743770250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             279769842150                       # Total energy per rank (pJ)
system.physmem_0.averagePower              692.623817                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   311776883750                       # Time in different power states
system.physmem_0.memoryStateTime::REF     13488020000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     78662661250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  542467800                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  295989375                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1483341600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                928473840                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            26382567120                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            60448758210                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           189331310250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             279412908195                       # Total energy per rank (pJ)
system.physmem_1.averagePower              691.740141                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   314432491250                       # Time in different power states
system.physmem_1.memoryStateTime::REF     13488020000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     76007072500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               219314839                       # Number of BP lookups
system.cpu.branchPred.condPredicted         219314839                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           8530231                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            123981217                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               121825604                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             98.261339                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                27068206                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1407908                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                        807862648                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          175941692                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1208657835                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   219314839                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          148893810                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     622000001                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                17769177                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                        227                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                92380                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles        735169                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles         1433                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles           29                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 170789403                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               2323822                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                       4                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples          807655519                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.784658                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.367182                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                417598750     51.71%     51.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 32531773      4.03%     55.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 31857083      3.94%     59.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 32716073      4.05%     63.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 26594170      3.29%     67.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 26933309      3.33%     70.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 35181908      4.36%     74.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 31423846      3.89%     78.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                172818607     21.40%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            807655519                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.271475                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.496118                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                120412218                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             371076736                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 225209960                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              82072017                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                8884588                       # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts             2132095724                       # Number of instructions handled by decode
system.cpu.rename.SquashCycles                8884588                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                152556291                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               150817488                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          41958                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 271423783                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             223931411                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2088526658                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                137354                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents              138380994                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               24891978                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               50561951                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2190720490                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5278322969                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3357144423                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups             60320                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1614040854                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                576679636                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               3187                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           2956                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 423114583                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            507122992                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           200812983                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads         229080264                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         68423458                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2023133283                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               22942                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1788928106                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            421261                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       494167524                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    833180412                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          22390                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     807655519                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.214964                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.070282                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           238829466     29.57%     29.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           123732265     15.32%     44.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           119115162     14.75%     59.64% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           107661207     13.33%     72.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            89581047     11.09%     84.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            60232277      7.46%     91.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            42307619      5.24%     96.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            18921199      2.34%     99.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             7275277      0.90%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       807655519                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                11512552     42.68%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               12355843     45.81%     88.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3105832     11.51%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass           2718297      0.15%      0.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1183078959     66.13%     66.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               370517      0.02%     66.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv               3881151      0.22%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 134      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                 67      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                 365      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.52% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            428492741     23.95%     90.48% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           170385875      9.52%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1788928106                       # Type of FU issued
system.cpu.iq.rate                           2.214396                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    26974227                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.015078                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         4412876800                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        2517572556                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1762303286                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads               30419                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes              69720                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses         5693                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1813170766                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                   13270                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads        186079397                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    123023075                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       212257                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       371984                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     51652797                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        22860                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1101                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                8884588                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                97906785                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               6199562                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2023156225                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            370486                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             507125232                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            200812983                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               7241                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1822287                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               3474512                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         371984                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        4845065                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      4137242                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8982307                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1769932780                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             423113153                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          18995326                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                             0                       # number of nop insts executed
system.cpu.iew.exec_refs                    590301691                       # number of memory reference insts executed
system.cpu.iew.exec_branches                168980249                       # Number of branches executed
system.cpu.iew.exec_stores                  167188538                       # Number of stores executed
system.cpu.iew.exec_rate                     2.190883                       # Inst execution rate
system.cpu.iew.wb_sent                     1766804374                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1762308979                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1339663552                       # num instructions producing a value
system.cpu.iew.wb_consumers                2049989844                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.181446                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.653498                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       494228972                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           8612841                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    740434686                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.064988                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.575030                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    276267324     37.31%     37.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    172135150     23.25%     60.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     56000087      7.56%     68.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     86333753     11.66%     79.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     25859703      3.49%     83.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     26527369      3.58%     86.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      9854605      1.33%     88.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      9004729      1.22%     89.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     78451966     10.60%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    740434686                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
system.cpu.commit.committedOps             1528988701                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      533262343                       # Number of memory references committed
system.cpu.commit.loads                     384102157                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  149758583                       # Number of branches committed
system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1526605509                       # Number of committed integer instructions.
system.cpu.commit.function_calls             17673145                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass      1819099      0.12%      0.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        989721889     64.73%     64.85% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          306834      0.02%     64.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv          3878536      0.25%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     65.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       384102157     25.12%     90.24% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      149160186      9.76%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1528988701                       # Class of committed instruction
system.cpu.commit.bw_lim_events              78451966                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   2685200393                       # The number of ROB reads
system.cpu.rob.rob_writes                  4113829657                       # The number of ROB writes
system.cpu.timesIdled                            2326                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          207129                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
system.cpu.committedOps                    1528988701                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.977004                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.977004                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.023537                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.023537                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2722489562                       # number of integer regfile reads
system.cpu.int_regfile_writes              1435790744                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      5969                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      521                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 596647275                       # number of cc regfile reads
system.cpu.cc_regfile_writes                405463698                       # number of cc regfile writes
system.cpu.misc_regfile_reads               971582048                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2530897                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4087.817920                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           381840179                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2534993                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            150.627705                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        1673396500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4087.817920                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998002                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998002                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           29                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          865                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         3173                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         772772413                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        772772413                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    233184165                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       233184165                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148172813                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148172813                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     381356978                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        381356978                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    381356978                       # number of overall hits
system.cpu.dcache.overall_hits::total       381356978                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2774343                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2774343                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       987389                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       987389                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      3761732                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3761732                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3761732                       # number of overall misses
system.cpu.dcache.overall_misses::total       3761732                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  59119368500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  59119368500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  31296279995                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  31296279995                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  90415648495                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  90415648495                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  90415648495                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  90415648495                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    235958508                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    235958508                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160202                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    385118710                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    385118710                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    385118710                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    385118710                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011758                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.011758                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006620                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.006620                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009768                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009768                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009768                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009768                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 24035.643287                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 24035.643287                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        10106                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets           15                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs              1086                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.305709                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     7.500000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2330787                       # number of writebacks
system.cpu.dcache.writebacks::total           2330787                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1009448                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1009448                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19379                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        19379                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1028827                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1028827                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1028827                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1028827                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764895                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1764895                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       968010                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       968010                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2732905                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2732905                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2732905                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2732905                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33550858500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  33550858500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  30073647496                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  30073647496                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  63624505996                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  63624505996                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  63624505996                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  63624505996                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007480                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007480                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006490                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006490                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007096                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.007096                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007096                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.007096                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements              6655                       # number of replacements
system.cpu.icache.tags.tagsinuse          1037.678215                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           170577740                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              8265                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          20638.565033                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1037.678215                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.506679                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.506679                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1610                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           50                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          326                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1153                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.786133                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         341785100                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        341785100                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    170580521                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       170580521                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     170580521                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        170580521                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    170580521                       # number of overall hits
system.cpu.icache.overall_hits::total       170580521                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       208882                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        208882                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       208882                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         208882                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       208882                       # number of overall misses
system.cpu.icache.overall_misses::total        208882                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1312211500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1312211500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1312211500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1312211500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1312211500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1312211500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    170789403                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    170789403                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    170789403                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    170789403                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    170789403                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    170789403                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001223                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.001223                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.001223                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.001223                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.001223                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.001223                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6282.070739                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  6282.070739                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  6282.070739                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  6282.070739                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  6282.070739                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  6282.070739                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          889                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    74.083333                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2585                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2585                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2585                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2585                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2585                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2585                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       206297                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       206297                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       206297                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       206297                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       206297                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       206297                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    989635000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    989635000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    989635000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    989635000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    989635000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    989635000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001208                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001208                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001208                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.001208                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001208                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.001208                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4797.137137                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4797.137137                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4797.137137                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  4797.137137                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4797.137137                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  4797.137137                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           353544                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29619.458392                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3891749                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           385874                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            10.085543                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle     189343942500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   242.518808                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8435.398201                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.639085                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007401                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.257428                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.903914                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32330                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1            4                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          215                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13379                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18648                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.986633                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         43295860                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        43295860                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks      2330787                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2330787                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         1834                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         1834                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       563915                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       563915                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         4843                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         4843                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1588207                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1588207                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         4843                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2152122                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2156965                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         4843                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2152122                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2156965                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data       196078                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total       196078                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       206573                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       206573                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3410                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         3410                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176298                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       176298                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3410                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       382871                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        386281                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3410                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       382871                       # number of overall misses
system.cpu.l2cache.overall_misses::total       386281                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     13890000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     13890000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16378927500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  16378927500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    280136500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    280136500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14178823000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  14178823000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    280136500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  30557750500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  30837887000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    280136500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  30557750500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  30837887000                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks      2330787                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2330787                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data       197912                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total       197912                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       770488                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       770488                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8253                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         8253                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1764505                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1764505                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         8253                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2534993                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2543246                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         8253                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2534993                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2543246                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990733                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990733                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268107                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.268107                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.413183                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.413183                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099914                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099914                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.413183                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.151034                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.151885                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.413183                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.151034                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.151885                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    70.839156                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    70.839156                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79288.810735                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79288.810735                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82151.466276                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82151.466276                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80425.319629                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80425.319629                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82151.466276                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79812.131240                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79832.782353                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82151.466276                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79812.131240                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79832.782353                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       294838                       # number of writebacks
system.cpu.l2cache.writebacks::total           294838                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total            2                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         1958                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         1958                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       196078                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total       196078                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206573                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       206573                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3408                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3408                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176298                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176298                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3408                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       382871                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       386279                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3408                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       382871                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       386279                       # number of overall MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   4323708271                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   4323708271                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14313197500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14313197500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    245909500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    245909500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12415843000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12415843000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    245909500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26729040500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  26974950000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    245909500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26729040500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  26974950000                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990733                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990733                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268107                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268107                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.412941                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.412941                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099914                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099914                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.412941                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151034                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.151884                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.412941                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151034                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.151884                       # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests      5476754                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2732107                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests       213805                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         3607                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3607                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp       1970799                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      2625625                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       253914                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq       197912                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp       197912                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       770488                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       770488                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       206297                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1764505                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       220789                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7985563                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           8206352                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       528000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311409920                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          311937920                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      551588                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      5830298                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.072755                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.259734                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            5406114     92.72%     92.72% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             424184      7.28%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5830298                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5097760193                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     309447487                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    3901446077                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             179703                       # Transaction distribution
system.membus.trans_dist::Writeback            294838                       # Transaction distribution
system.membus.trans_dist::CleanEvict            57117                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           196128                       # Transaction distribution
system.membus.trans_dist::UpgradeResp          196128                       # Transaction distribution
system.membus.trans_dist::ReadExReq            206523                       # Transaction distribution
system.membus.trans_dist::ReadExResp           206523                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        179705                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1516665                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1516665                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1516665                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43588096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43588096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                43588096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            934311                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  934311    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              934311                       # Request fanout histogram
system.membus.reqLayer0.occupancy          2245481708                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.6                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2435298904                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)

---------- End Simulation Statistics   ----------