blob: a158074c5ba6e43fedf023415407d909a3ff1ee7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.141089 # Number of seconds simulated
sim_ticks 141089296500 # Number of ticks simulated
final_tick 141089296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 83115 # Simulator instruction rate (inst/s)
host_op_rate 83115 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 29414893 # Simulator tick rate (ticks/s)
host_mem_usage 223012 # Number of bytes of host memory used
host_seconds 4796.53 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
system.physmem.bytes_read::total 468992 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 214976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 214976 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1523688 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1800392 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3324079 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1523688 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1523688 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1523688 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1800392 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3324079 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7328 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 468992 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 465 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 464 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 518 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 520 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 382 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 398 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 457 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 444 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 407 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 457 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 588 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 397 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 529 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 418 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 396 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 488 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 141089244500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 7328 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
system.physmem.writePktSize::2 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.writePktSize::6 0 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 4661 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1890 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 520 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.totQLat 39617295 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 175175295 # Sum of mem lat for all requests
system.physmem.totBusLat 29312000 # Total cycles spent in databus access
system.physmem.totBankLat 106246000 # Total cycles spent in bank access
system.physmem.avgQLat 5406.29 # Average queueing delay per request
system.physmem.avgBankLat 14498.64 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
system.physmem.avgMemAccLat 23904.93 # Average memory access latency
system.physmem.avgRdBW 3.32 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.32 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
system.physmem.readRowHits 6442 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19253444.94 # Average gap between requests
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754611 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754632 # DTB read accesses
system.cpu.dtb.write_hits 73521102 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73521137 # DTB write accesses
system.cpu.dtb.data_hits 168275713 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275769 # DTB accesses
system.cpu.itb.fetch_hits 49091192 # ITB hits
system.cpu.itb.fetch_misses 88817 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 49180009 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 282178594 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.lookups 53863325 # Number of BP lookups
system.cpu.branch_predictor.condPredicted 30909619 # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect 16029157 # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups 33388385 # Number of BTB lookups
system.cpu.branch_predictor.BTBHits 15622160 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 19 # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct 46.789205 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29654286 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24209039 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280812298 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 440148157 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119908557 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 220105038 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100451904 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168699560 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14461353 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 1567145 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 16028498 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 28559053 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 35.948370 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205751378 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 2124332 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 281883987 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7632 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13336617 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 268841977 # Number of cycles cpu stages are processed.
system.cpu.activity 95.273696 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed
system.cpu.comNops 23089775 # Number of Nop instructions committed
system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
system.cpu.comInts 112239074 # Number of Integer instructions committed
system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
system.cpu.cpi 0.707810 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.707810 # CPI: Total CPI of All Threads
system.cpu.ipc 1.412809 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.412809 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 78396963 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 203781631 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.217254 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 108683745 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 173494849 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.484058 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 104474173 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177704421 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 62.975869 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 183396585 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98782009 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 35.006911 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 92487828 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189690766 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.223656 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1982 # number of replacements
system.cpu.icache.tagsinuse 1831.235862 # Cycle average of tags in use
system.cpu.icache.total_refs 49086683 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 3910 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12554.138875 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1831.235862 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.894158 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.894158 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 49086683 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 49086683 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 49086683 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 49086683 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 49086683 # number of overall hits
system.cpu.icache.overall_hits::total 49086683 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses
system.cpu.icache.overall_misses::total 4508 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 196984000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 196984000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 196984000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 196984000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 196984000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 196984000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 49091191 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 49091191 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 49091191 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 49091191 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 49091191 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 49091191 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43696.539485 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 43696.539485 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 43696.539485 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 43696.539485 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 43696.539485 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 598 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 598 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 598 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 598 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 598 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3910 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3910 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3910 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3910 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3910 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3910 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 172100500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 172100500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 172100500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 172100500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 172100500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 172100500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44015.473146 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44015.473146 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44015.473146 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 44015.473146 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.tagsinuse 3285.555145 # Cycle average of tags in use
system.cpu.dcache.total_refs 168254416 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40523.703276 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 3285.555145 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.802137 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.802137 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 94753185 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 94753185 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 73501231 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 73501231 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 168254416 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168254416 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168254416 # number of overall hits
system.cpu.dcache.overall_hits::total 168254416 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1304 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1304 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 19498 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 19498 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 20802 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 20802 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 20802 # number of overall misses
system.cpu.dcache.overall_misses::total 20802 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 64930000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 64930000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 710139000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 710139000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 775069000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 775069000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 775069000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 775069000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49792.944785 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 49792.944785 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36421.120115 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 36421.120115 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37259.350062 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37259.350062 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 37259.350062 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 15899 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 535 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.717757 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
system.cpu.dcache.writebacks::total 649 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 354 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16296 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 16296 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 16650 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 16650 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 16650 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 16650 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48068500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 48068500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153897000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 153897000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 201965500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 201965500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 201965500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 201965500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50598.421053 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50598.421053 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48062.773267 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48062.773267 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48642.943160 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 48642.943160 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48642.943160 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48642.943160 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3908.656926 # Cycle average of tags in use
system.cpu.l2cache.total_refs 760 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.161119 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 370.653922 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 2910.300742 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 627.702262 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.011311 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.088815 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.119283 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 551 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 674 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 551 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 734 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 551 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
system.cpu.l2cache.overall_hits::total 734 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 3359 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3359 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 162633000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45642500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 208275500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150126000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 150126000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 162633000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 195768500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 358401500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 162633000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 195768500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 358401500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3910 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 4857 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 3910 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 8062 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 3910 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8062 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.859079 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.861231 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.859079 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.908956 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.859079 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.908956 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48417.088419 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55391.383495 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49790.939517 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47734.817170 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47734.817170 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48417.088419 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49324.389015 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 48908.501638 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48417.088419 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49324.389015 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 48908.501638 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3359 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3359 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 120134545 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35298214 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155432759 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111138322 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111138322 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120134545 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 146436536 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 266571081 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120134545 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 146436536 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 266571081 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.861231 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.908956 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.859079 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.908956 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35764.973206 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42837.638350 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37158.202008 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35338.099205 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35338.099205 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35764.973206 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36895.070799 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36377.057997 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|