path: root/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.233526                       # Number of seconds simulated
sim_ticks                                233525789500                       # Number of ticks simulated
final_tick                               233525789500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 279317                       # Simulator instruction rate (inst/s)
host_op_rate                                   279317                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              163615265                       # Simulator tick rate (ticks/s)
host_mem_usage                                 255720                       # Number of bytes of host memory used
host_seconds                                  1427.29                       # Real time elapsed on the host
sim_insts                                   398664651                       # Number of instructions simulated
sim_ops                                     398664651                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            249280                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            254592                       # Number of bytes read from this memory
system.physmem.bytes_read::total               503872                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       249280                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          249280                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3895                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               3978                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  7873                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              1067462                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1090209                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2157672                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1067462                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1067462                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1067462                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1090209                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2157672                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          7873                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        7873                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   503872                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    503872                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 548                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 675                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 473                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 633                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 475                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 477                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 563                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 560                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 471                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 437                       # Per bank write bursts
system.physmem.perBankRdBursts::10                354                       # Per bank write bursts
system.physmem.perBankRdBursts::11                323                       # Per bank write bursts
system.physmem.perBankRdBursts::12                430                       # Per bank write bursts
system.physmem.perBankRdBursts::13                556                       # Per bank write bursts
system.physmem.perBankRdBursts::14                473                       # Per bank write bursts
system.physmem.perBankRdBursts::15                425                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    233525688500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    7873                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      6857                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       948                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        68                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         1541                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      326.852693                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     195.480715                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     331.694198                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            535     34.72%     34.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          344     22.32%     57.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          186     12.07%     69.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          104      6.75%     75.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           66      4.28%     80.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           53      3.44%     83.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           28      1.82%     85.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           39      2.53%     87.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          186     12.07%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1541                       # Bytes accessed per row activation
system.physmem.totQLat                       52273750                       # Total ticks spent queuing
system.physmem.totMemAccLat                 199892500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     39365000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        6639.62                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25389.62                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.16                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.16                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       6330                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.40                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                     29661588.78                       # Average gap between requests
system.physmem.pageHitRate                      80.40                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    6804000                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    3712500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  34327800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            15252731520                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             5982776145                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           134867232750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             156147584715                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.653337                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   224361889750                       # Time in different power states
system.physmem_0.memoryStateTime::REF      7797920000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      1365674000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    4845960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    2644125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  27058200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            15252731520                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             5743132470                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           135077446500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             156107858775                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.483223                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   224713608000                       # Time in different power states
system.physmem_1.memoryStateTime::REF      7797920000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      1013955750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                45912937                       # Number of BP lookups
system.cpu.branchPred.condPredicted          26702744                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            565787                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             25186730                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                18811780                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             74.689251                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 8285572                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                323                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         2249877                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            2235903                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            13974                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       111495                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                     95338457                       # DTB read hits
system.cpu.dtb.read_misses                        116                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                 95338573                       # DTB read accesses
system.cpu.dtb.write_hits                    73578378                       # DTB write hits
system.cpu.dtb.write_misses                       849                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                73579227                       # DTB write accesses
system.cpu.dtb.data_hits                    168916835                       # DTB hits
system.cpu.dtb.data_misses                        965                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                168917800                       # DTB accesses
system.cpu.itb.fetch_hits                    96959231                       # ITB hits
system.cpu.itb.fetch_misses                      1239                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                96960470                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                  215                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    233525789500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        467051579                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   398664651                       # Number of instructions committed
system.cpu.committedOps                     398664651                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       2289293                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.171540                       # CPI: cycles per instruction
system.cpu.ipc                               0.853577                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass            23123356      5.80%      5.80% # Class of committed instruction
system.cpu.op_class_0::IntAlu               141652555     35.53%     41.33% # Class of committed instruction
system.cpu.op_class_0::IntMult                2124322      0.53%     41.86% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     41.86% # Class of committed instruction
system.cpu.op_class_0::FloatAdd              35620060      8.93%     50.80% # Class of committed instruction
system.cpu.op_class_0::FloatCmp               7072549      1.77%     52.57% # Class of committed instruction
system.cpu.op_class_0::FloatCvt               2735231      0.69%     53.26% # Class of committed instruction
system.cpu.op_class_0::FloatMult             16498021      4.14%     57.40% # Class of committed instruction
system.cpu.op_class_0::FloatDiv               1563283      0.39%     57.79% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     57.79% # Class of committed instruction
system.cpu.op_class_0::MemRead               94754510     23.77%     81.56% # Class of committed instruction
system.cpu.op_class_0::MemWrite              73520764     18.44%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                398664651                       # Class of committed instruction
system.cpu.tickCycles                       455740556                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        11311023                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements               771                       # number of replacements
system.cpu.dcache.tags.tagsinuse          3291.966637                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           167817023                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          40292.202401                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  3291.966637                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.803703                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.803703                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           26                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          216                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         3113                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         335652191                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        335652191                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     94302223                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        94302223                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     73514800                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       73514800                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     167817023                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        167817023                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    167817023                       # number of overall hits
system.cpu.dcache.overall_hits::total       167817023                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         1061                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          1061                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         5929                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         5929                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         6990                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           6990                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         6990                       # number of overall misses
system.cpu.dcache.overall_misses::total          6990                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     77930500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     77930500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    429190000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    429190000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    507120500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    507120500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    507120500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    507120500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     94303284                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     94303284                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    167824013                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    167824013                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    167824013                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    167824013                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000011                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000011                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000081                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000081                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000042                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000042                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73450.047125                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 73450.047125                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72388.261090                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 72388.261090                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72549.427754                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 72549.427754                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72549.427754                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 72549.427754                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks          654                       # number of writebacks
system.cpu.dcache.writebacks::total               654                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data           92                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total           92                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2733                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         2733                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         2825                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         2825                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         2825                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         2825                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          969                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          969                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3196                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         3196                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         4165                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         4165                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     70280500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     70280500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    239912500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    239912500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    310193000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    310193000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    310193000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    310193000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72528.895769                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72528.895769                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75066.489362                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75066.489362                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74476.110444                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74476.110444                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74476.110444                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74476.110444                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements              3193                       # number of replacements
system.cpu.icache.tags.tagsinuse          1919.750364                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            96954060                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              5171                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          18749.576484                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1919.750364                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.937378                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.937378                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           87                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          208                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          396                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1287                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         193923633                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        193923633                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     96954060                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        96954060                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      96954060                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         96954060                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     96954060                       # number of overall hits
system.cpu.icache.overall_hits::total        96954060                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         5171                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          5171                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         5171                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           5171                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         5171                       # number of overall misses
system.cpu.icache.overall_misses::total          5171                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    318040500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    318040500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    318040500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    318040500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    318040500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    318040500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     96959231                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     96959231                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     96959231                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     96959231                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     96959231                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     96959231                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000053                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000053                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000053                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000053                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000053                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000053                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61504.641269                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61504.641269                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61504.641269                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61504.641269                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61504.641269                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61504.641269                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks         3193                       # number of writebacks
system.cpu.icache.writebacks::total              3193                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5171                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         5171                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         5171                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         5171                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         5171                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         5171                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312869500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    312869500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312869500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    312869500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312869500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    312869500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60504.641269                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60504.641269                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60504.641269                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 60504.641269                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60504.641269                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60504.641269                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         4425.384656                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs               4801                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             5273                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.910487                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   372.164909                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3411.179805                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   642.039942                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.011358                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.104101                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.019594                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.135052                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         5273                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          613                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4442                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160919                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           114871                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          114871                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks          654                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total          654                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks         3193                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total         3193                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           61                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1276                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         1276                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data          126                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total          126                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         1276                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data          187                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total            1463                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         1276                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data          187                       # number of overall hits
system.cpu.l2cache.overall_hits::total           1463                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data         3137                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         3137                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3895                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         3895                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data          841                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total          841                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3895                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         3978                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          7873                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3895                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         3978                       # number of overall misses
system.cpu.l2cache.overall_misses::total         7873                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    234589500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    234589500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    291713500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    291713500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     67354500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total     67354500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    291713500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    301944000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    593657500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    291713500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    301944000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    593657500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks          654                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total          654                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks         3193                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total         3193                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         3198                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         3198                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5171                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         5171                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          967                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total          967                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         5171                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         4165                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         9336                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         5171                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         4165                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         9336                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.980926                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.980926                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.753239                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.753239                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.869700                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.869700                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.753239                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.955102                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.843295                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.753239                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.955102                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.843295                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74781.479120                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74781.479120                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74894.351733                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74894.351733                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80088.585018                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80088.585018                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74894.351733                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75903.469080                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75404.229646                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74894.351733                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75903.469080                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75404.229646                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3137                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         3137                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3895                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3895                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          841                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total          841                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3895                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         3978                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         7873                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3895                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         3978                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         7873                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    203219500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    203219500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    252763500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    252763500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     58944500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     58944500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    252763500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    262164000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    514927500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    252763500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    262164000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    514927500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.980926                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980926                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.753239                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.753239                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.869700                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.869700                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.753239                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.843295                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.753239                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.843295                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.479120                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.479120                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64894.351733                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64894.351733                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70088.585018                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70088.585018                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.351733                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65903.469080                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65404.229646                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.351733                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65903.469080                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65404.229646                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests        13300                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests         3964                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp          6138                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty          654                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean         3193                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict          117                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         3198                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         3198                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq         5171                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq          967                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13535                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9101                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             22636                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       535296                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total             843712                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                     0                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples         9336                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0               9336    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total           9336                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy       10497000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       7756500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       6247999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.membus.pwrStateResidencyTicks::UNDEFINED 233525789500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp               4736                       # Transaction distribution
system.membus.trans_dist::ReadExReq              3137                       # Transaction distribution
system.membus.trans_dist::ReadExResp             3137                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          4736                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15746                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  15746                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       503872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  503872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples              7873                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    7873    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                7873                       # Request fanout histogram
system.membus.reqLayer0.occupancy             9219000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           41801750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------