path: root/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.080354                       # Number of seconds simulated
sim_ticks                                 80354154000                       # Number of ticks simulated
final_tick                                80354154000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 172564                       # Simulator instruction rate (inst/s)
host_op_rate                                   172564                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               36920064                       # Simulator tick rate (ticks/s)
host_mem_usage                                 226504                       # Number of bytes of host memory used
host_seconds                                  2176.44                       # Real time elapsed on the host
sim_insts                                   375574808                       # Number of instructions simulated
sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            222976                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            255424                       # Number of bytes read from this memory
system.physmem.bytes_read::total               478400                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       222976                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          222976                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3484                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               3991                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  7475                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              2774916                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3178728                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 5953644                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2774916                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2774916                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2774916                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3178728                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                5953644                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    103401614                       # DTB read hits
system.cpu.dtb.read_misses                      88552                       # DTB read misses
system.cpu.dtb.read_acv                         48603                       # DTB read access violations
system.cpu.dtb.read_accesses                103490166                       # DTB read accesses
system.cpu.dtb.write_hits                    79056152                       # DTB write hits
system.cpu.dtb.write_misses                      1601                       # DTB write misses
system.cpu.dtb.write_acv                            2                       # DTB write access violations
system.cpu.dtb.write_accesses                79057753                       # DTB write accesses
system.cpu.dtb.data_hits                    182457766                       # DTB hits
system.cpu.dtb.data_misses                      90153                       # DTB misses
system.cpu.dtb.data_acv                         48605                       # DTB access violations
system.cpu.dtb.data_accesses                182547919                       # DTB accesses
system.cpu.itb.fetch_hits                    52578444                       # ITB hits
system.cpu.itb.fetch_misses                       446                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses                52578890                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                  215                       # Number of system calls
system.cpu.numCycles                        160708310                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 52055858                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           30270064                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            1609565                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              28583053                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 24291253                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  9363483                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                1125                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           53630506                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      462761975                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    52055858                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           33654736                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      81569260                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 7805922                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               19227823                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  182                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          8640                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                  52578444                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                632985                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          160593743                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.881569                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.314206                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 79024483     49.21%     49.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  4373999      2.72%     51.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  7277585      4.53%     56.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  5624285      3.50%     59.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 12451588      7.75%     67.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  8090347      5.04%     72.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  5701462      3.55%     76.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1906860      1.19%     77.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 36143134     22.51%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            160593743                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.323915                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.879515                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 59159628                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              14701180                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  76777373                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               3802489                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                6153073                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              9767212                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                  4329                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              457201252                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 12277                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                6153073                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 62463630                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 4784250                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         400809                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  77384574                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               9407407                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              451419869                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    14                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  20713                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               7782416                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands           295098377                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             593658097                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        314398187                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         279259910                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 35566048                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              38393                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            348                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  27305396                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            107006158                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            81864884                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           8914753                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          6402170                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  416586090                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 336                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 407940469                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1092011                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        40751586                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     19838559                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            121                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     160593743                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.540202                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.007855                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            32107491     19.99%     19.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            26532573     16.52%     36.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            26024058     16.20%     52.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            24782303     15.43%     68.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            21577160     13.44%     81.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15465247      9.63%     91.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             8675795      5.40%     96.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             4109702      2.56%     99.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1319414      0.82%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       160593743                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                   35836      0.30%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.30% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                 73145      0.62%      0.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                  5467      0.05%      0.96% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                  3221      0.03%      0.99% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult              1851348     15.57%     16.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv               1774625     14.92%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     31.48% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                5106562     42.94%     74.43% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3040891     25.57%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             158120657     38.76%     38.77% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2126534      0.52%     39.29% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     39.29% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd            33463281      8.20%     47.49% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp             7848056      1.92%     49.42% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt             2840409      0.70%     50.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult           16567576      4.06%     54.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv             1592675      0.39%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.57% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            105294166     25.81%     80.38% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            80053534     19.62%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              407940469                       # Type of FU issued
system.cpu.iq.rate                           2.538391                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    11891095                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.029149                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          648130283                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         270005016                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    237809508                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           341327504                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes          187383841                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses    162964934                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              245490516                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses               174307467                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         14797790                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     12251671                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       123751                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        50882                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      8344155                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       260839                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked             3                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                6153073                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 2493888                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                367103                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           441513906                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            235069                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             107006158                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             81864884                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                336                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    120                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                    76                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          50882                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1249323                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       568752                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1818075                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             403380721                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             103538845                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           4559748                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                      24927480                       # number of nop insts executed
system.cpu.iew.exec_refs                    182596628                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 47226669                       # Number of branches executed
system.cpu.iew.exec_stores                   79057783                       # Number of stores executed
system.cpu.iew.exec_rate                     2.510018                       # Inst execution rate
system.cpu.iew.wb_sent                      401610425                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     400774442                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 195308199                       # num instructions producing a value
system.cpu.iew.wb_consumers                 273451305                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.493800                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.714234                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        42890401                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1605306                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    154440670                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.581345                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.965853                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     58870445     38.12%     38.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     23396206     15.15%     53.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     13280012      8.60%     61.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     11680215      7.56%     69.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      8466998      5.48%     74.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      5501467      3.56%     78.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      5150112      3.33%     81.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3370011      2.18%     83.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     24725204     16.01%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    154440670                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      168275216                       # Number of memory references committed
system.cpu.commit.loads                      94754487                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                   44587533                       # Number of branches committed
system.cpu.commit.fp_insts                  155295106                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 316365839                       # Number of committed integer instructions.
system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              24725204                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    571267473                       # The number of ROB reads
system.cpu.rob.rob_writes                   889277309                       # The number of ROB writes
system.cpu.timesIdled                            3039                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          114567                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             375574808                       # Number of Instructions Simulated
system.cpu.cpi                               0.427900                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.427900                       # CPI: Total CPI of All Threads
system.cpu.ipc                               2.336997                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         2.336997                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                402957504                       # number of integer regfile reads
system.cpu.int_regfile_writes               172619998                       # number of integer regfile writes
system.cpu.fp_regfile_reads                 158343155                       # number of floating regfile reads
system.cpu.fp_regfile_writes                105226626                       # number of floating regfile writes
system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.icache.replacements                   2218                       # number of replacements
system.cpu.icache.tagsinuse               1836.523631                       # Cycle average of tags in use
system.cpu.icache.total_refs                 52573018                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   4149                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               12671.250422                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1836.523631                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.896740                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.896740                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     52573018                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        52573018                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      52573018                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         52573018                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     52573018                       # number of overall hits
system.cpu.icache.overall_hits::total        52573018                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         5426                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          5426                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         5426                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           5426                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         5426                       # number of overall misses
system.cpu.icache.overall_misses::total          5426                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    168571000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    168571000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    168571000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    168571000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    168571000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    168571000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     52578444                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     52578444                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     52578444                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     52578444                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     52578444                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     52578444                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000103                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000103                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000103                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000103                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000103                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000103                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31067.268706                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 31067.268706                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 31067.268706                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 31067.268706                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 31067.268706                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 31067.268706                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1277                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1277                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1277                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1277                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1277                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1277                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4149                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         4149                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         4149                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         4149                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         4149                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         4149                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    129086500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    129086500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    129086500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    129086500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    129086500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    129086500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000079                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000079                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000079                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000079                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31112.677754                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31112.677754                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31112.677754                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 31112.677754                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31112.677754                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 31112.677754                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                    788                       # number of replacements
system.cpu.dcache.tagsinuse               3297.853996                       # Cycle average of tags in use
system.cpu.dcache.total_refs                161841661                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   4190                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               38625.694749                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    3297.853996                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.805140                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.805140                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     88341162                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        88341162                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     73500481                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       73500481                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           18                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           18                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data     161841643                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        161841643                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    161841643                       # number of overall hits
system.cpu.dcache.overall_hits::total       161841643                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         1802                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          1802                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        20248                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        20248                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data        22050                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total          22050                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data        22050                       # number of overall misses
system.cpu.dcache.overall_misses::total         22050                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data     62316500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total     62316500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    625415500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    625415500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    687732000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    687732000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    687732000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    687732000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     88342964                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     88342964                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           18                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           18                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    161863693                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    161863693                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    161863693                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    161863693                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000020                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000020                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000275                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000275                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000136                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000136                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000136                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000136                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34581.853496                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34581.853496                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30887.766693                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30887.766693                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31189.659864                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31189.659864                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31189.659864                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31189.659864                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         7500                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs         7500                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks          667                       # number of writebacks
system.cpu.dcache.writebacks::total               667                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          813                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          813                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        17047                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        17047                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        17860                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        17860                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        17860                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        17860                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data          989                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total          989                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3201                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         3201                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         4190                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4190                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         4190                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4190                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     35672500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     35672500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    129053000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    129053000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    164725500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    164725500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    164725500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    164725500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000011                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000044                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36069.261881                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36069.261881                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40316.463605                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40316.463605                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39313.961814                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 39313.961814                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39313.961814                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 39313.961814                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              4035.335685                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                     887                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  4877                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.181874                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks   371.767101                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   3005.985586                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    657.582998                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.011345                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.091735                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.020068                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.123149                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst          665                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data          130                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total            795                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks          667                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total          667                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           69                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           69                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst          665                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data          199                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total             864                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst          665                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data          199                       # number of overall hits
system.cpu.l2cache.overall_hits::total            864                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3484                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data          859                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4343                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         3132                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         3132                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3484                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         3991                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          7475                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3484                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         3991                       # number of overall misses
system.cpu.l2cache.overall_misses::total         7475                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    124255000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     34500500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    158755500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    125685500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    125685500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    124255000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    160186000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    284441000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    124255000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    160186000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    284441000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         4149                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data          989                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total         5138                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks          667                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total          667                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         3201                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         3201                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         4149                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         4190                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total         8339                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         4149                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         4190                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total         8339                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.839720                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.868554                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.845271                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.978444                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.978444                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.839720                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.952506                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.896390                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.839720                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.952506                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.896390                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35664.466131                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40163.562282                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 36554.340318                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 40129.469987                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 40129.469987                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35664.466131                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40136.807818                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 38052.307692                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35664.466131                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40136.807818                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 38052.307692                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs         3500                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                1                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs         3500                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3484                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          859                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4343                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3132                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         3132                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3484                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         3991                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         7475                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3484                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         3991                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         7475                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    112975000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     31822500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    144797500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115935000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115935000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    112975000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    147757500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    260732500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    112975000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    147757500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    260732500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.839720                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.868554                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.845271                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.978444                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.978444                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.839720                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.952506                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.896390                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.839720                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.952506                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.896390                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32426.808266                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37045.983702                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33340.432880                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37016.283525                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37016.283525                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32426.808266                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37022.676021                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34880.602007                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32426.808266                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37022.676021                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34880.602007                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------