path: root/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
final_tick                               227445516000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate                                 153700                       # Simulator instruction rate (inst/s)
host_mem_usage                                 303376                       # Number of bytes of host memory used
host_op_rate                                   196498                       # Simulator op (including micro ops) rate (op/s)
host_seconds                                  1776.44                       # Real time elapsed on the host
host_tick_rate                              128034740                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   273037854                       # Number of instructions simulated
sim_ops                                     349065592                       # Number of ops (including micro ops) simulated
sim_seconds                                  0.227446                       # Number of seconds simulated
sim_ticks                                227445516000                       # Number of ticks simulated
system.clk_domain.clock                          1000                       # Clock period in ticks
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             83.362247                       # BTB Hit Percentage
system.cpu.branchPred.BTBHits                16723894                       # Number of BTB hits
system.cpu.branchPred.BTBLookups             20061712                       # Number of BTB lookups
system.cpu.branchPred.RASInCorrect                121                       # Number of incorrect RAS predictions.
system.cpu.branchPred.condIncorrect           1671536                       # Number of conditional branches incorrect
system.cpu.branchPred.condPredicted          21059526                       # Number of conditional branches predicted
system.cpu.branchPred.lookups                35363260                       # Number of BP lookups
system.cpu.branchPred.usedRAS                 6617396                       # Number of times the RAS was used to get a target.
system.cpu.committedInsts                   273037854                       # Number of instructions committed
system.cpu.committedOps                     349065592                       # Number of ops (including micro ops) committed
system.cpu.cpi                               1.666037                       # CPI: cycles per instruction
system.cpu.dcache.LoadLockedReq_accesses::cpu.inst        10895                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits::cpu.inst        10895                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
system.cpu.dcache.ReadReq_accesses::cpu.inst     95145110                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     95145110                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 61749.740048                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 61749.740048                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.734497                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61620.734497                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits::cpu.inst     95143025                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        95143025                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency::cpu.inst    128748208                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    128748208                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses::cpu.inst         2085                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          2085                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst          424                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          424                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst    102352040                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    102352040                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.000017                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000017                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst         1661                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total         1661                       # number of ReadReq MSHR misses
system.cpu.dcache.StoreCondReq_accesses::cpu.inst        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::cpu.inst        10895                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses::cpu.inst     82052677                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68469.206380                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 68469.206380                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68654.108392                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68654.108392                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits::cpu.inst     82047473                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       82047473                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency::cpu.inst    356313750                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    356313750                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.000063                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000063                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses::cpu.inst         5204                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         5204                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst         2344                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         2344                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst    196350750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    196350750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst         2860                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         2860                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses::cpu.inst    177197787                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    177197787                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66547.120044                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66547.120044                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 66070.070781                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66070.070781                       # average overall mshr miss latency
system.cpu.dcache.demand_hits::cpu.inst     177190498                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        177190498                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency::cpu.inst    485061958                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    485061958                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate::cpu.inst     0.000041                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000041                       # miss rate for demand accesses
system.cpu.dcache.demand_misses::cpu.inst         7289                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           7289                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits::cpu.inst         2768                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         2768                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst    298702790                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    298702790                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000026                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses::cpu.inst         4521                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4521                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses::cpu.inst    177197787                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    177197787                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66547.120044                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66547.120044                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 66070.070781                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66070.070781                       # average overall mshr miss latency
system.cpu.dcache.overall_hits::cpu.inst    177190498                       # number of overall hits
system.cpu.dcache.overall_hits::total       177190498                       # number of overall hits
system.cpu.dcache.overall_miss_latency::cpu.inst    485061958                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    485061958                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate::cpu.inst     0.000041                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000041                       # miss rate for overall accesses
system.cpu.dcache.overall_misses::cpu.inst         7289                       # number of overall misses
system.cpu.dcache.overall_misses::total          7289                       # number of overall misses
system.cpu.dcache.overall_mshr_hits::cpu.inst         2768                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         2768                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst    298702790                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    298702790                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.000026                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000026                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses::cpu.inst         4521                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4521                       # number of overall MSHR misses
system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           11                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          674                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         2436                       # Occupied blocks per task id
system.cpu.dcache.tags.avg_refs          39197.586375                       # Average number of references to valid blocks.
system.cpu.dcache.tags.data_accesses        354443675                       # Number of data accesses
system.cpu.dcache.tags.occ_blocks::cpu.inst  3089.554835                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.inst     0.754286                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.754286                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         3161                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.771729                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.replacements              1360                       # number of replacements
system.cpu.dcache.tags.sampled_refs              4521                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.tag_accesses         354443675                       # Number of tag accesses
system.cpu.dcache.tags.tagsinuse          3089.554835                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           177212288                       # Total number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks::writebacks         1013                       # number of writebacks
system.cpu.dcache.writebacks::total              1013                       # number of writebacks
system.cpu.discardedOps                       6932970                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.icache.ReadReq_accesses::cpu.inst     77471042                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     77471042                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17858.870336                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17858.870336                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15825.006083                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15825.006083                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits::cpu.inst     77429612                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        77429612                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency::cpu.inst    739892998                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    739892998                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000535                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000535                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses::cpu.inst        41430                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         41430                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    655630002                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    655630002                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000535                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        41430                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        41430                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses::cpu.inst     77471042                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     77471042                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17858.870336                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17858.870336                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15825.006083                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 15825.006083                       # average overall mshr miss latency
system.cpu.icache.demand_hits::cpu.inst      77429612                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         77429612                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency::cpu.inst    739892998                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    739892998                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate::cpu.inst     0.000535                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000535                       # miss rate for demand accesses
system.cpu.icache.demand_misses::cpu.inst        41430                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          41430                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    655630002                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    655630002                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000535                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses::cpu.inst        41430                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        41430                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses::cpu.inst     77471042                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     77471042                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17858.870336                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17858.870336                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15825.006083                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 15825.006083                       # average overall mshr miss latency
system.cpu.icache.overall_hits::cpu.inst     77429612                       # number of overall hits
system.cpu.icache.overall_hits::total        77429612                       # number of overall hits
system.cpu.icache.overall_miss_latency::cpu.inst    739892998                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    739892998                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate::cpu.inst     0.000535                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000535                       # miss rate for overall accesses
system.cpu.icache.overall_misses::cpu.inst        41430                       # number of overall misses
system.cpu.icache.overall_misses::total         41430                       # number of overall misses
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    655630002                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    655630002                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000535                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses::cpu.inst        41430                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        41430                       # number of overall MSHR misses
system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           87                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          288                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1478                       # Occupied blocks per task id
system.cpu.icache.tags.avg_refs           1868.971300                       # Average number of references to valid blocks.
system.cpu.icache.tags.data_accesses        154983513                       # Number of data accesses
system.cpu.icache.tags.occ_blocks::cpu.inst  1927.026996                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.940931                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.940931                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1941                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.947754                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.replacements             39488                       # number of replacements
system.cpu.icache.tags.sampled_refs             41429                       # Sample count of references to valid blocks.
system.cpu.icache.tags.tag_accesses         154983513                       # Number of tag accesses
system.cpu.icache.tags.tagsinuse          1927.026996                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            77429612                       # Total number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.idleCycles                         4029946                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.ipc                               0.600227                       # IPC: instructions per cycle
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses::cpu.inst         2860                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         2860                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67967.563291                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67967.563291                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55399.173699                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55399.173699                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits::cpu.inst           16                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst    193299750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    193299750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.994406                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.994406                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses::cpu.inst         2844                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2844                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst    157555250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    157555250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.994406                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994406                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst         2844                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         2844                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses::cpu.inst        43091                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        43091                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68852.642487                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68852.642487                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56391.699770                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56391.699770                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits::cpu.inst        38266                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          38266                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    332214000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    332214000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.111972                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.111972                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses::cpu.inst         4825                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4825                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           42                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           42                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    269721500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    269721500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.110998                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.110998                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4783                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4783                       # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses::writebacks         1013                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total         1013                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits::writebacks         1013                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total         1013                       # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses::cpu.inst        45951                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        45951                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68524.416482                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68524.416482                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56021.600892                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56021.600892                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits::cpu.inst        38282                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           38282                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency::cpu.inst    525513750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    525513750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.166895                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.166895                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses::cpu.inst         7669                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          7669                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits::cpu.inst           42                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           42                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    427276750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    427276750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.165981                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.165981                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         7627                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         7627                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses::cpu.inst        45951                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        45951                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68524.416482                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68524.416482                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56021.600892                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56021.600892                       # average overall mshr miss latency
system.cpu.l2cache.overall_hits::cpu.inst        38282                       # number of overall hits
system.cpu.l2cache.overall_hits::total          38282                       # number of overall hits
system.cpu.l2cache.overall_miss_latency::cpu.inst    525513750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    525513750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.166895                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.166895                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses::cpu.inst         7669                       # number of overall misses
system.cpu.l2cache.overall_misses::total         7669                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits::cpu.inst           42                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           42                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    427276750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    427276750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.165981                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.165981                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         7627                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         7627                       # number of overall MSHR misses
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2           40                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1262                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4305                       # Occupied blocks per task id
system.cpu.l2cache.tags.avg_refs             6.727368                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.data_accesses          384272                       # Number of data accesses
system.cpu.l2cache.tags.occ_blocks::writebacks   356.812936                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3883.048925                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.010889                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.118501                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.129390                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         5700                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.173950                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.sampled_refs             5700                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.tag_accesses           384272                       # Number of tag accesses
system.cpu.l2cache.tags.tagsinuse         4239.861860                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              38346                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.numCycles                        454891032                       # number of cpu cycles simulated
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.tickCycles                       450861086                       # Number of cycles that the CPU actually ticked
system.cpu.toL2Bus.data_through_bus           3005632                       # Total data (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        82859                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10055                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             92914                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy       24495000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      62845998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       7514710                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.throughput                13214734                       # Throughput (bytes/s)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2651456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       354176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total        3005632                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.trans_dist::ReadReq          43091                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         43090                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback         1013                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         2860                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         2860                       # Transaction distribution
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.membus.data_through_bus                 488128                       # Total data (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15254                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  15254                       # Packet count per connected master and slave (bytes)
system.membus.reqLayer0.occupancy             8910000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           71341750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.throughput                      2146132                       # Throughput (bytes/s)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       488128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total              488128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.trans_dist::ReadReq                4783                       # Transaction distribution
system.membus.trans_dist::ReadResp               4783                       # Transaction distribution
system.membus.trans_dist::ReadExReq              2844                       # Transaction distribution
system.membus.trans_dist::ReadExResp             2844                       # Transaction distribution
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgGap                     29821084.57                       # Average gap between requests
system.physmem.avgMemAccLat                  25580.41                       # Average memory access latency per DRAM burst
system.physmem.avgQLat                        6830.41                       # Average queueing delay per DRAM burst
system.physmem.avgRdBW                           2.15                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.15                       # Average system read bandwidth in MiByte/s
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.bw_inst_read::cpu.inst          974721                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             974721                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst              2146132                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2146132                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2146132                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2146132                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytesPerActivate::samples         1544                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      315.689119                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     184.950751                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.584238                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            593     38.41%     38.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          326     21.11%     59.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          172     11.14%     70.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           76      4.92%     75.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           71      4.60%     80.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           58      3.76%     83.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           38      2.46%     86.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           28      1.81%     88.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          182     11.79%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1544                       # Bytes accessed per row activation
system.physmem.bytesReadDRAM                   488128                       # Total number of bytes read from DRAM
system.physmem.bytesReadSys                    488128                       # Total read bytes from the system interface side
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.bytes_inst_read::cpu.inst       221696                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          221696                       # Number of instructions bytes read from this memory
system.physmem.bytes_read::cpu.inst            488128                       # Number of bytes read from this memory
system.physmem.bytes_read::total               488128                       # Number of bytes read from this memory
system.physmem.memoryStateTime::IDLE     217468466000                       # Time in different power states
system.physmem.memoryStateTime::REF        7594860000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT        2381096500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.num_reads::cpu.inst               7627                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  7627                       # Number of read requests responded to by this memory
system.physmem.pageHitRate                      79.70                       # Row buffer hit rate, read and write combined
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.perBankRdBursts::0                 637                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 850                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 633                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 541                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 470                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 350                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 175                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 229                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 210                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 309                       # Per bank write bursts
system.physmem.perBankRdBursts::10                346                       # Per bank write bursts
system.physmem.perBankRdBursts::11                428                       # Per bank write bursts
system.physmem.perBankRdBursts::12                552                       # Per bank write bursts
system.physmem.perBankRdBursts::13                714                       # Per bank write bursts
system.physmem.perBankRdBursts::14                639                       # Per bank write bursts
system.physmem.perBankRdBursts::15                544                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.rdQLenPdf::0                      6680                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       887                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.readBursts                        7627                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    7627                       # Read request sizes (log2)
system.physmem.readReqs                          7627                       # Number of read requests accepted
system.physmem.readRowHitRate                   79.70                       # Row buffer hit rate for reads
system.physmem.readRowHits                       6079                       # Number of row buffer hits during reads
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.totBusLat                     38135000                       # Total ticks spent in databus transfers
system.physmem.totGap                    227445412000                       # Total gap between requests
system.physmem.totMemAccLat                 195101750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat                       52095500                       # Total ticks spent queuing
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.voltage_domain.voltage                       1                       # Voltage in Volts

---------- End Simulation Statistics   ----------