path: root/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.216140                       # Number of seconds simulated
sim_ticks                                216139917000                       # Number of ticks simulated
final_tick                               216139917000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 173188                       # Simulator instruction rate (inst/s)
host_op_rate                                   207931                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              137097336                       # Simulator tick rate (ticks/s)
host_mem_usage                                 323040                       # Number of bytes of host memory used
host_seconds                                  1576.54                       # Real time elapsed on the host
sim_insts                                   273037857                       # Number of instructions simulated
sim_ops                                     327812214                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            219136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            266368                       # Number of bytes read from this memory
system.physmem.bytes_read::total               485504                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       219136                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          219136                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3424                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               4162                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  7586                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              1013862                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1232387                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2246249                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1013862                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1013862                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1013862                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1232387                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2246249                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          7586                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        7586                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   485504                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    485504                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 630                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 843                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 628                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 541                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 466                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 173                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 228                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 209                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 311                       # Per bank write bursts
system.physmem.perBankRdBursts::10                342                       # Per bank write bursts
system.physmem.perBankRdBursts::11                428                       # Per bank write bursts
system.physmem.perBankRdBursts::12                553                       # Per bank write bursts
system.physmem.perBankRdBursts::13                706                       # Per bank write bursts
system.physmem.perBankRdBursts::14                638                       # Per bank write bursts
system.physmem.perBankRdBursts::15                541                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    216139680500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    7586                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      6624                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       901                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         1523                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      318.319107                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     188.795582                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.243204                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            551     36.18%     36.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          346     22.72%     58.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          176     11.56%     70.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           81      5.32%     75.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           75      4.92%     80.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           50      3.28%     83.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           32      2.10%     86.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           28      1.84%     87.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          184     12.08%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1523                       # Bytes accessed per row activation
system.physmem.totQLat                       53007250                       # Total ticks spent queuing
system.physmem.totMemAccLat                 195244750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     37930000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        6987.51                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25737.51                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.25                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.25                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       6060                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.88                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                     28491916.75                       # Average gap between requests
system.physmem.pageHitRate                      79.88                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    5004720                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    2730750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  30022200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            14117117040                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             5648540400                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           124728404250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             144531819360                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.699173                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   207494790250                       # Time in different power states
system.physmem_0.memoryStateTime::REF      7217340000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      1426657250                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    6509160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    3551625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  29062800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            14117117040                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             5781551040                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           124611728250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             144549519915                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.781068                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   207298156250                       # Time in different power states
system.physmem_1.memoryStateTime::REF      7217340000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      1623563250                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                33139216                       # Number of BP lookups
system.cpu.branchPred.condPredicted          17107199                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1560655                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             17520877                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                15610870                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             89.098679                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 6611023                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu.numCycles                        432279834                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   273037857                       # Number of instructions committed
system.cpu.committedOps                     327812214                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       4207498                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.583223                       # CPI: cycles per instruction
system.cpu.ipc                               0.631623                       # IPC: instructions per cycle
system.cpu.tickCycles                       428628441                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                         3651393                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements              1354                       # number of replacements
system.cpu.dcache.tags.tagsinuse          3085.737950                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           168771151                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          37413.245622                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  3085.737950                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.753354                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.753354                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           17                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          672                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         2432                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         337561379                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        337561379                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     86638362                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        86638362                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     82047459                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       82047459                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        63540                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         63540                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168685821                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168685821                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168749361                       # number of overall hits
system.cpu.dcache.overall_hits::total       168749361                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         2059                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          2059                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         5218                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         5218                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data            6                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total            6                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data         7277                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           7277                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         7283                       # number of overall misses
system.cpu.dcache.overall_misses::total          7283                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data    136967456                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    136967456                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    400451000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    400451000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    537418456                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    537418456                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    537418456                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    537418456                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     86640421                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     86640421                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data        63546                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total        63546                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    168693098                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    168693098                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    168756644                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    168756644                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000064                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000064                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000094                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.000094                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66521.348227                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66521.348227                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76744.154849                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76744.154849                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73851.649856                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73851.649856                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73790.808183                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73790.808183                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks         1010                       # number of writebacks
system.cpu.dcache.writebacks::total              1010                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          422                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          422                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2348                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         2348                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         2770                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         2770                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         2770                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         2770                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1637                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total         1637                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2870                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         2870                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         4507                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4507                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         4511                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    108888792                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    108888792                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    220256750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    220256750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       320750                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       320750                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    329145542                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    329145542                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    329466292                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    329466292                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000063                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000063                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66517.282834                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66517.282834                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76744.512195                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76744.512195                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73029.851786                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73029.851786                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73036.198626                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73036.198626                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             36928                       # number of replacements
system.cpu.icache.tags.tagsinuse          1924.841098                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            73108223                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             38865                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           1881.081256                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1924.841098                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.939864                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.939864                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           88                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1487                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         146333043                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        146333043                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     73108223                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        73108223                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      73108223                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         73108223                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     73108223                       # number of overall hits
system.cpu.icache.overall_hits::total        73108223                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        38866                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         38866                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        38866                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          38866                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        38866                       # number of overall misses
system.cpu.icache.overall_misses::total         38866                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    728130248                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    728130248                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    728130248                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    728130248                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    728130248                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    728130248                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     73147089                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     73147089                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     73147089                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     73147089                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     73147089                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     73147089                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000531                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000531                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000531                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000531                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000531                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000531                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18734.375753                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18734.375753                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18734.375753                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18734.375753                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18734.375753                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18734.375753                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38866                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        38866                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        38866                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        38866                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        38866                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        38866                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    668381252                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    668381252                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    668381252                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    668381252                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    668381252                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    668381252                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000531                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000531                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000531                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000531                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17197.068183                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17197.068183                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17197.068183                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17197.068183                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17197.068183                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17197.068183                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         4199.211257                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              35810                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             5648                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.340297                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   353.787736                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3167.125698                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   678.297823                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.010797                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096653                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.020700                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.128150                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         5648                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1252                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4261                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172363                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           363614                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          363614                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        35440                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data          291                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          35731                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks         1010                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total         1010                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        35440                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data          307                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           35747                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        35440                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data          307                       # number of overall hits
system.cpu.l2cache.overall_hits::total          35747                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3426                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         1350                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4776                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2854                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2854                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3426                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         4204                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          7630                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3426                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         4204                       # number of overall misses
system.cpu.l2cache.overall_misses::total         7630                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    257404250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    104503500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    361907750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    217183750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    217183750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    257404250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    321687250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    579091500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    257404250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    321687250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    579091500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        38866                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data         1641                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        40507                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks         1010                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total         1010                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         2870                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         2870                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        38866                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         4511                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        43377                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        38866                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         4511                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        43377                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.088149                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.822669                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.117906                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994425                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.994425                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.088149                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.931944                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.175900                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.088149                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.931944                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.175900                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75132.589025                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        77410                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75776.329564                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76098.020322                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76098.020322                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75132.589025                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76519.326832                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75896.657929                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75132.589025                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76519.326832                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75896.657929                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           42                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           44                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           42                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           44                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           42                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           44                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3424                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1308                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4732                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2854                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         2854                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3424                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         4162                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         7586                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3424                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         4162                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         7586                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    214398750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     85427750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    299826500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    181482250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    181482250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    214398750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    266910000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    481308750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    214398750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    266910000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    481308750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.088098                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.797075                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.116819                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088098                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.174885                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088098                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.174885                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62616.457360                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65311.735474                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63361.475063                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63588.735109                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63588.735109                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62616.457360                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64130.225853                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63446.974690                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62616.457360                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64130.225853                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63446.974690                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq          40507                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         40506                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback         1010                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         2870                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         2870                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77731                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10032                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             87763                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2487360                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total            2840704                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples        44387                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              44387    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total          44387                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy       23203500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      59023248                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       7574708                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.membus.trans_dist::ReadReq                4732                       # Transaction distribution
system.membus.trans_dist::ReadResp               4732                       # Transaction distribution
system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15172                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  15172                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  485504                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples              7586                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    7586    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                7586                       # Request fanout histogram
system.membus.reqLayer0.occupancy             8848500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           40266750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------