path: root/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.216865                       # Number of seconds simulated
sim_ticks                                216864820000                       # Number of ticks simulated
final_tick                               216864820000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 175540                       # Simulator instruction rate (inst/s)
host_op_rate                                   210755                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              139425507                       # Simulator tick rate (ticks/s)
host_mem_usage                                 321524                       # Number of bytes of host memory used
host_seconds                                  1555.42                       # Real time elapsed on the host
sim_insts                                   273037856                       # Number of instructions simulated
sim_ops                                     327812213                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            219008                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            266368                       # Number of bytes read from this memory
system.physmem.bytes_read::total               485376                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       219008                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          219008                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3422                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               4162                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  7584                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              1009883                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1228267                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2238150                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         1009883                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            1009883                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             1009883                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1228267                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2238150                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          7584                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        7584                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   485376                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    485376                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 630                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 843                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 628                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 541                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 466                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 172                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 228                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 209                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 311                       # Per bank write bursts
system.physmem.perBankRdBursts::10                342                       # Per bank write bursts
system.physmem.perBankRdBursts::11                428                       # Per bank write bursts
system.physmem.perBankRdBursts::12                553                       # Per bank write bursts
system.physmem.perBankRdBursts::13                706                       # Per bank write bursts
system.physmem.perBankRdBursts::14                637                       # Per bank write bursts
system.physmem.perBankRdBursts::15                541                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    216864583500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    7584                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      6626                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       898                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         1523                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      317.772817                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     188.476979                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     330.358112                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            549     36.05%     36.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          352     23.11%     59.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          179     11.75%     70.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           73      4.79%     75.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           70      4.60%     80.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           53      3.48%     83.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           37      2.43%     86.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           29      1.90%     88.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          181     11.88%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1523                       # Bytes accessed per row activation
system.physmem.totQLat                       53728750                       # Total ticks spent queuing
system.physmem.totMemAccLat                 195928750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     37920000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        7084.49                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  25834.49                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           2.24                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        2.24                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.02                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       6056                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   79.85                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                     28595013.65                       # Average gap between requests
system.physmem.pageHitRate                      79.85                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                    5027400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                    2743125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  29952000                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            14164413120                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             5668320825                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           125145525750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             145015982220                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.698913                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   208188918000                       # Time in different power states
system.physmem_0.memoryStateTime::REF      7241520000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      1432738500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    6486480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    3539250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  29031600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            14164413120                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             5831746380                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           125002170000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             145037386830                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.797614                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   207947266000                       # Time in different power states
system.physmem_1.memoryStateTime::REF      7241520000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      1674122750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                33219592                       # Number of BP lookups
system.cpu.branchPred.condPredicted          17177082                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1581285                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             17974979                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                15661112                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             87.127290                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 6612085                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu.numCycles                        433729640                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   273037856                       # Number of instructions committed
system.cpu.committedOps                     327812213                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       4054235                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.588533                       # CPI: cycles per instruction
system.cpu.ipc                               0.629512                       # IPC: instructions per cycle
system.cpu.tickCycles                       430193160                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                         3536480                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements              1354                       # number of replacements
system.cpu.dcache.tags.tagsinuse          3085.768991                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           168782225                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          37415.700510                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  3085.768991                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.753362                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.753362                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          672                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         2432                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         337583521                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        337583521                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     86712977                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        86712977                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     82047458                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       82047458                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     168760435                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        168760435                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    168760435                       # number of overall hits
system.cpu.dcache.overall_hits::total       168760435                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         2061                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          2061                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data         5219                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total         5219                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data         7280                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total           7280                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data         7280                       # number of overall misses
system.cpu.dcache.overall_misses::total          7280                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data    137684956                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    137684956                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    400150250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    400150250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    537835206                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    537835206                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    537835206                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    537835206                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     86715038                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     86715038                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    168767715                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    168767715                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    168767715                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    168767715                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000064                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000064                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73878.462363                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73878.462363                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks         1010                       # number of writebacks
system.cpu.dcache.writebacks::total              1010                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          420                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          420                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2349                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total         2349                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data         2769                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total         2769                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data         2769                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total         2769                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1641                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total         1641                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2870                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         2870                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         4511                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4511                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         4511                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    109745542                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    109745542                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    219964750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    219964750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    329710292                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    329710292                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    329710292                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    329710292                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             36897                       # number of replacements
system.cpu.icache.tags.tagsinuse          1924.852609                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            73252005                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             38834                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           1886.285343                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1924.852609                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.939869                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.939869                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           88                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1487                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         146620514                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        146620514                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     73252005                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        73252005                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      73252005                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         73252005                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     73252005                       # number of overall hits
system.cpu.icache.overall_hits::total        73252005                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        38835                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         38835                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        38835                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          38835                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        38835                       # number of overall misses
system.cpu.icache.overall_misses::total         38835                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    728456748                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    728456748                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    728456748                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    728456748                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    728456748                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    728456748                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     73290840                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     73290840                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     73290840                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     73290840                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     73290840                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     73290840                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000530                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000530                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000530                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000530                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000530                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000530                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18757.737814                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18757.737814                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38835                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        38835                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        38835                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        38835                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        38835                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        38835                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    668757252                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    668757252                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    668757252                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    668757252                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    668757252                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    668757252                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000530                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000530                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000530                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000530                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17220.477713                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17220.477713                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17220.477713                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17220.477713                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17220.477713                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17220.477713                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         4197.194159                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              35781                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             5646                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             6.337407                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   353.722028                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  3165.177467                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   678.294664                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.010795                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096594                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.020700                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.128088                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         5646                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1252                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4259                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172302                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           363364                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          363364                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        35411                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data          291                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          35702                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks         1010                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total         1010                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        35411                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data          307                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           35718                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        35411                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data          307                       # number of overall hits
system.cpu.l2cache.overall_hits::total          35718                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3424                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         1350                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4774                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2854                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2854                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3424                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         4204                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          7628                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3424                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         4204                       # number of overall misses
system.cpu.l2cache.overall_misses::total         7628                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    258115750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    105039500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    363155250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    216891750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    216891750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    258115750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    321931250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    580047000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    258115750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    321931250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    580047000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        38835                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data         1641                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        40476                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks         1010                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total         1010                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         2870                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         2870                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        38835                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         4511                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        43346                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        38835                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         4511                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        43346                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.088168                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.822669                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.117946                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994425                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.994425                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.088168                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.931944                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.175979                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.088168                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.931944                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.175979                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75384.272780                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77807.037037                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76069.386259                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75995.707779                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75995.707779                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75384.272780                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.366794                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76041.819612                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75384.272780                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.366794                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76041.819612                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           42                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           44                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           42                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           44                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           42                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           44                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3422                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1308                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4730                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2854                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         2854                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3422                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         4162                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         7584                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3422                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         4162                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         7584                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    215130250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     85732250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    300862500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    181193250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    181193250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    215130250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    266925500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    482055750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    215130250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    266925500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    482055750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.088116                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.797075                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.116859                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088116                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.174964                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088116                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.174964                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq          40476                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         40475                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback         1010                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         2870                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         2870                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77669                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10032                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             87701                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2485376                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total            2838720                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples        44356                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3              44356    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total          44356                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy       23188000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      58975248                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       7577708                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.membus.trans_dist::ReadReq                4730                       # Transaction distribution
system.membus.trans_dist::ReadResp               4730                       # Transaction distribution
system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15168                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  15168                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  485376                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples              7584                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                    7584    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total                7584                       # Request fanout histogram
system.membus.reqLayer0.occupancy             8969500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           40264250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)

---------- End Simulation Statistics   ----------