path: root/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.068540                       # Number of seconds simulated
sim_ticks                                 68540241500                       # Number of ticks simulated
final_tick                                68540241500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 122061                       # Simulator instruction rate (inst/s)
host_op_rate                                   156050                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               30641006                       # Simulator tick rate (ticks/s)
host_mem_usage                                 321880                       # Number of bytes of host memory used
host_seconds                                  2236.88                       # Real time elapsed on the host
sim_insts                                   273036725                       # Number of instructions simulated
sim_ops                                     349064449                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            193920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            272448                       # Number of bytes read from this memory
system.physmem.bytes_read::total               466368                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       193920                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          193920                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3030                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               4257                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  7287                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              2829287                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3975008                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 6804295                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2829287                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2829287                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2829287                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3975008                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6804295                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          7287                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        7287                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   466368                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    466368                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              2                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 604                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 802                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 607                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 525                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 444                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 161                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 221                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 206                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 292                       # Per bank write bursts
system.physmem.perBankRdBursts::10                324                       # Per bank write bursts
system.physmem.perBankRdBursts::11                416                       # Per bank write bursts
system.physmem.perBankRdBursts::12                533                       # Per bank write bursts
system.physmem.perBankRdBursts::13                685                       # Per bank write bursts
system.physmem.perBankRdBursts::14                612                       # Per bank write bursts
system.physmem.perBankRdBursts::15                506                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     68540041000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    7287                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      4301                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2168                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       588                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       170                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         1441                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      322.087439                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     187.561369                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     340.705535                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127            517     35.88%     35.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255          362     25.12%     61.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          132      9.16%     70.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           71      4.93%     75.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           61      4.23%     79.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           42      2.91%     82.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           35      2.43%     84.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           26      1.80%     86.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          195     13.53%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1441                       # Bytes accessed per row activation
system.physmem.totQLat                       60227500                       # Total ticks spent queuing
system.physmem.totMemAccLat                 196858750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     36435000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        8265.06                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27015.06                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           6.80                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        6.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.17                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       5834                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   80.06                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      9405796.76                       # Average gap between requests
system.physmem.pageHitRate                      80.06                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE      64419207500                       # Time in different power states
system.physmem.memoryStateTime::REF        2288520000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT        1827118750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                      6804295                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                4468                       # Transaction distribution
system.membus.trans_dist::ReadResp               4468                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq              2819                       # Transaction distribution
system.membus.trans_dist::ReadExResp             2819                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14578                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  14578                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       466368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total              466368                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                 466368                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy             8924000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           67911998                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                35427097                       # Number of BP lookups
system.cpu.branchPred.condPredicted          21222481                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1662305                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             19504890                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                16830620                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             86.289233                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 6785276                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               8391                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu.numCycles                        137080484                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           39013094                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      318011666                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    35427097                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           23615896                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      70957700                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6891338                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               21536315                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  110                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1697                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           56                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  37608451                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                511125                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          136726497                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.983044                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.454276                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 66399200     48.56%     48.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  6788638      4.97%     53.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  5707530      4.17%     57.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  6111990      4.47%     62.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4922665      3.60%     65.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  4080012      2.98%     68.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  3180881      2.33%     71.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  4139139      3.03%     74.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 35396442     25.89%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            136726497                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.258440                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.319890                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 45526376                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              16684464                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  66829825                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               2537018                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                5148814                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              7346336                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 69128                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              401912579                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                214046                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                5148814                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 51079671                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 1913308                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         333807                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  63753347                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              14497550                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              394307650                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    25                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1657315                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              10195595                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            22429                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           432708181                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            2738145852                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1575813049                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         200323476                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             384566193                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 48141988                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              11963                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          11962                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  36553940                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            103619662                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            91398989                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           4293575                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5309451                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  384641768                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               22898                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 374271543                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1203075                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        34859337                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    100548351                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            778                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     136726497                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.737374                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.024550                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            25150398     18.39%     18.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            19938048     14.58%     32.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            20598425     15.07%     48.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            18168946     13.29%     61.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            24025170     17.57%     78.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15741501     11.51%     90.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             8821837      6.45%     96.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             3366776      2.46%     99.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              915396      0.67%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       136726497                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                    8454      0.05%      0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   4686      0.03%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.07% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd             46141      0.26%      0.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp              3549      0.02%      0.35% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt               438      0.00%      0.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 3      0.00%      0.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc           186673      1.05%      1.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult             3981      0.02%      1.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc        241129      1.36%      2.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.80% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                9262679     52.30%     55.10% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               7952866     44.90%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             126495771     33.80%     33.80% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2175574      0.58%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    1      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         6778108      1.81%     36.19% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.19% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         8473024      2.26%     38.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         3429632      0.92%     39.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv         1595745      0.43%     39.80% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       20862309      5.57%     45.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult        7172511      1.92%     47.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc      7129172      1.90%     49.19% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.24% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            101679299     27.17%     76.41% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            88305111     23.59%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              374271543                       # Type of FU issued
system.cpu.iq.rate                           2.730305                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    17710599                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.047320                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          654796096                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         289211293                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    250149926                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           249387161                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes          130326745                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses    118060008                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              263377407                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses               128604735                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         11093990                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      8970914                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       108859                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14127                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      9023406                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       175522                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1863                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                5148814                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  279698                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 35585                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           384666248                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            872586                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             103619662                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             91398989                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              11864                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    344                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   288                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14127                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1301679                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       370144                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1671823                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             370317109                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             100386827                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3954434                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          1582                       # number of nop insts executed
system.cpu.iew.exec_refs                    187618668                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 32015275                       # Number of branches executed
system.cpu.iew.exec_stores                   87231841                       # Number of stores executed
system.cpu.iew.exec_rate                     2.701458                       # Inst execution rate
system.cpu.iew.wb_sent                      368883883                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     368209934                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 183051685                       # num instructions producing a value
system.cpu.iew.wb_consumers                 363776414                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.686086                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.503198                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        35601258                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1593594                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    131577683                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.652920                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.658674                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     34743119     26.41%     26.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     28469178     21.64%     48.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     13363377     10.16%     58.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     11438386      8.69%     66.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     13773451     10.47%     77.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7412867      5.63%     82.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      3865563      2.94%     85.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3891482      2.96%     88.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     14620260     11.11%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    131577683                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            273037337                       # Number of instructions committed
system.cpu.commit.committedOps              349065061                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      177024331                       # Number of memory references committed
system.cpu.commit.loads                      94648748                       # Number of loads committed
system.cpu.commit.membars                       11033                       # Number of memory barriers committed
system.cpu.commit.branches                   30563497                       # Number of branches committed
system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 279584611                       # Number of committed integer instructions.
system.cpu.commit.function_calls              6225112                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        116648967     33.42%     33.42% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         2145845      0.61%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     34.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd      6594343      1.89%     35.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     35.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp      7943502      2.28%     38.20% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt      3118180      0.89%     39.09% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv      1563217      0.45%     39.54% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc     19652356      5.63%     45.17% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult      7136937      2.04%     47.21% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc      7062098      2.02%     49.24% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt       175285      0.05%     49.29% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        94648748     27.11%     76.40% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       82375583     23.60%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         349065061                       # Class of committed instruction
system.cpu.commit.bw_lim_events              14620260                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    501621219                       # The number of ROB reads
system.cpu.rob.rob_writes                   774485510                       # The number of ROB writes
system.cpu.timesIdled                            6746                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          353987                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   273036725                       # Number of Instructions Simulated
system.cpu.committedOps                     349064449                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.502059                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.502059                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.991799                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.991799                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1770130874                       # number of integer regfile reads
system.cpu.int_regfile_writes               233038396                       # number of integer regfile writes
system.cpu.fp_regfile_reads                 188133896                       # number of floating regfile reads
system.cpu.fp_regfile_writes                132498519                       # number of floating regfile writes
system.cpu.misc_regfile_reads              1201060026                       # number of misc regfile reads
system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                20063659                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          17609                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         17609                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback         1041                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         2837                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         2837                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31648                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10285                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             41933                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1012608                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       362304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total        1374912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus           1374912                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus          256                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy       11785500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      24279239                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       7466709                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements             13936                       # number of replacements
system.cpu.icache.tags.tagsinuse          1847.607729                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            37591137                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             15825                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           2375.427299                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1847.607729                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.902152                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.902152                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1889                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           89                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1525                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.922363                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          75232724                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         75232724                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     37591137                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        37591137                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      37591137                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         37591137                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     37591137                       # number of overall hits
system.cpu.icache.overall_hits::total        37591137                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        17312                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         17312                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        17312                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          17312                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        17312                       # number of overall misses
system.cpu.icache.overall_misses::total         17312                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    452091985                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    452091985                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    452091985                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    452091985                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    452091985                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    452091985                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     37608449                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     37608449                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     37608449                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     37608449                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     37608449                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     37608449                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000460                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000460                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000460                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000460                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000460                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000460                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26114.370668                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 26114.370668                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 26114.370668                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 26114.370668                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 26114.370668                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 26114.370668                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          970                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                19                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    51.052632                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1486                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1486                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1486                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1486                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1486                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1486                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15826                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        15826                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        15826                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        15826                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        15826                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        15826                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    356931509                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    356931509                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    356931509                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    356931509                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    356931509                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    356931509                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000421                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000421                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000421                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22553.488500                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22553.488500                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22553.488500                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 22553.488500                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22553.488500                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 22553.488500                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         3938.278477                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              13178                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             5394                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.443085                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   377.930800                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2772.496816                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   787.850861                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.011534                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084610                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.024043                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.120187                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         5394                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1247                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4004                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.164612                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           180111                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          180111                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        12781                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data          302                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          13083                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks         1041                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total         1041                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           18                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           18                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        12781                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data          320                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           13101                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        12781                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data          320                       # number of overall hits
system.cpu.l2cache.overall_hits::total          13101                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3041                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         1481                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4522                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2819                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2819                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3041                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         4300                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          7341                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3041                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         4300                       # number of overall misses
system.cpu.l2cache.overall_misses::total         7341                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    213267000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    109185750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    322452750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    198902000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    198902000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    213267000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    308087750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    521354750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    213267000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    308087750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    521354750                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        15822                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data         1783                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        17605                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks         1041                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total         1041                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            2                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            2                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         2837                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         2837                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        15822                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         4620                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        20442                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        15822                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         4620                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        20442                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.192201                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.830623                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.256859                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993655                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.993655                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192201                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.930736                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.359114                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192201                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.930736                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.359114                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70130.549161                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73724.341661                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71307.551968                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70557.644555                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70557.644555                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70130.549161                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71648.313953                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71019.581801                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70130.549161                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71648.313953                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71019.581801                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           43                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           54                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           43                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           54                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           43                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           54                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3030                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1438                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4468                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2819                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         2819                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3030                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         4257                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         7287                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3030                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         4257                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         7287                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    174561000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     88459500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    263020500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        20002                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        20002                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    163883500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    163883500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    174561000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    252343000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    426904000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    174561000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    252343000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    426904000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191505                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.806506                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253792                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993655                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993655                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191505                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.921429                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.356472                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191505                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.921429                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.356472                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57610.891089                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61515.646732                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58867.614145                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58135.331678                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58135.331678                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57610.891089                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59277.190510                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58584.328256                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57610.891089                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59277.190510                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58584.328256                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements              1423                       # number of replacements
system.cpu.dcache.tags.tagsinuse          3106.690369                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           170987022                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              4620                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          37010.177922                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  3106.690369                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.758469                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.758469                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         3197                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          683                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         2448                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.780518                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         342028974                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        342028974                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     88933648                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        88933648                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     82031473                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       82031473                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10994                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10994                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     170965121                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        170965121                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    170965121                       # number of overall hits
system.cpu.dcache.overall_hits::total       170965121                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         3973                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          3973                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        21192                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        21192                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data        25165                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total          25165                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data        25165                       # number of overall misses
system.cpu.dcache.overall_misses::total         25165                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data    236002703                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    236002703                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   1249306876                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   1249306876                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       170250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       170250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   1485309579                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   1485309579                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   1485309579                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   1485309579                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     88937621                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     88937621                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10996                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10996                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    170990286                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    170990286                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    170990286                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    170990286                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000045                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000258                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000258                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000182                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000182                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000147                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000147                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000147                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000147                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59401.636798                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 59401.636798                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58951.815591                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 58951.815591                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85125                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85125                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59022.832466                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59022.832466                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59022.832466                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59022.832466                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        25911                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1248                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               444                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              13                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    58.358108                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets           96                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks         1041                       # number of writebacks
system.cpu.dcache.writebacks::total              1041                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2189                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         2189                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18354                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        18354                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        20543                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        20543                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        20543                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        20543                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1784                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total         1784                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2838                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         2838                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         4622                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4622                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         4622                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4622                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    114103043                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    114103043                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    201967248                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    201967248                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    316070291                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    316070291                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    316070291                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    316070291                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63959.104821                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63959.104821                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71165.344609                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71165.344609                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68383.879489                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68383.879489                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68383.879489                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68383.879489                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------