path: root/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.071124                       # Number of seconds simulated
sim_ticks                                 71123520500                       # Number of ticks simulated
final_tick                                71123520500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 165652                       # Simulator instruction rate (inst/s)
host_op_rate                                   211776                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               43149002                       # Simulator tick rate (ticks/s)
host_mem_usage                                 241844                       # Number of bytes of host memory used
host_seconds                                  1648.32                       # Real time elapsed on the host
sim_insts                                   273048466                       # Number of instructions simulated
sim_ops                                     349076190                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            194944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            272832                       # Number of bytes read from this memory
system.physmem.bytes_read::total               467776                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       194944                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          194944                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3046                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               4263                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  7309                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              2740922                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3836031                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 6576952                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2740922                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2740922                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2740922                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3836031                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6576952                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          7309                       # Total number of read requests seen
system.physmem.writeReqs                            0                       # Total number of write requests seen
system.physmem.cpureqs                           7309                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                       467776                       # Total number of bytes read from memory
system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd                 467776                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                   346                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                   470                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                   514                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                   578                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                   477                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                   456                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                   440                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                   507                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                   480                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                   494                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                  484                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                  551                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                  365                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                  416                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                  368                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                  363                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                     0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                    0                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                    0                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                     71123348000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                    7309                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                      0                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                      4384                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2130                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       552                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       174                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        67                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                       38077286                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat                 170549286                       # Sum of mem lat for all requests
system.physmem.totBusLat                     29236000                       # Total cycles spent in databus access
system.physmem.totBankLat                   103236000                       # Total cycles spent in bank access
system.physmem.avgQLat                        5209.64                       # Average queueing delay per request
system.physmem.avgBankLat                    14124.50                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  23334.15                       # Average memory access latency
system.physmem.avgRdBW                           6.58                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                   6.58                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.04                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
system.physmem.readRowHits                       6380                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.29                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      9730927.35                       # Average gap between requests
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu.numCycles                        142247042                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                 43100384                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted           21816758                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect            2115490                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups              28214597                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                 17877846                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                  6960493                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                7483                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles           41104486                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      329097721                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    43100384                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           24838339                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      73741038                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 8424830                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               20890852                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  101                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          3376                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           52                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  39439386                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                697861                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          142038328                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.976886                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.453881                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 68979513     48.56%     48.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  7395782      5.21%     53.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  5795573      4.08%     57.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  6270161      4.41%     62.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4963047      3.49%     65.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  4315752      3.04%     68.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  3304919      2.33%     71.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  4334607      3.05%     74.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 36678974     25.82%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            142038328                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.302997                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.313565                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 47965638                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              16109831                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  69363004                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               2371211                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                6228644                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              7501471                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 70557                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              414890822                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                218836                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                6228644                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 53736634                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 1580220                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         347679                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  65886950                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              14258201                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              404388597                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   136                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1669522                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              10203430                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              860                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           443737755                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            2388674830                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1302452182                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups        1086222648                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             384584986                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 59152769                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              14467                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          14465                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  35681480                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            105493757                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            93214934                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           4606734                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5678105                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  392069014                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               25544                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 378019437                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1377395                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        42071369                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    110527513                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           1062                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     142038328                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.661390                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.043453                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            29008018     20.42%     20.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            20551186     14.47%     34.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            20935508     14.74%     49.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            18224796     12.83%     62.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            24071271     16.95%     79.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15985787     11.25%     90.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             9045864      6.37%     97.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             3293540      2.32%     99.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              922358      0.65%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       142038328                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                    9132      0.05%      0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   4698      0.03%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd             45614      0.25%      0.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.33% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp              7807      0.04%      0.37% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt               399      0.00%      0.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 3      0.00%      0.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc           193826      1.08%      1.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult             4889      0.03%      1.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc        240972      1.34%      2.82% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.82% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                9466915     52.66%     55.48% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               8004617     44.52%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             128267116     33.93%     33.93% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2174674      0.58%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         6840592      1.81%     36.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         8692743      2.30%     38.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         3457219      0.91%     39.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv         1621907      0.43%     39.96% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       21346208      5.65%     45.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult        7171870      1.90%     47.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc      7135741      1.89%     49.39% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            102459140     27.10%     76.54% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            88676941     23.46%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              378019437                       # Type of FU issued
system.cpu.iq.rate                           2.657485                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    17978872                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.047561                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          666289235                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         301587031                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    252300909                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           251144234                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes          132592793                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses    118832927                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              266512180                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses               129486129                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         10875090                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     10842660                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       119827                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14278                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     10836994                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        19866                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1167                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                6228644                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                   80063                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                  4890                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           392103714                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1113019                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             105493757                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             93214934                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              14372                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    353                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   361                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14278                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1696490                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       500488                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              2196978                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             373371007                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             101101213                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           4648430                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9156                       # number of nop insts executed
system.cpu.iew.exec_refs                    188456752                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 38701393                       # Number of branches executed
system.cpu.iew.exec_stores                   87355539                       # Number of stores executed
system.cpu.iew.exec_rate                     2.624807                       # Inst execution rate
system.cpu.iew.wb_sent                      371934669                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     371133836                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 184775670                       # num instructions producing a value
system.cpu.iew.wb_consumers                 367646771                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.609079                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.502590                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        43027028                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           24482                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           2045711                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    135809685                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.570338                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.654112                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     38417531     28.29%     28.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     29199317     21.50%     49.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     13525216      9.96%     59.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     11128430      8.19%     67.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     13789447     10.15%     78.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7275712      5.36%     83.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      3957925      2.91%     86.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3970991      2.92%     89.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     14545116     10.71%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    135809685                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            273049078                       # Number of instructions committed
system.cpu.commit.committedOps              349076802                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      177029037                       # Number of memory references committed
system.cpu.commit.loads                      94651097                       # Number of loads committed
system.cpu.commit.membars                       11033                       # Number of memory barriers committed
system.cpu.commit.branches                   36549060                       # Number of branches committed
system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 279594003                       # Number of committed integer instructions.
system.cpu.commit.function_calls              6225112                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              14545116                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    513365876                       # The number of ROB reads
system.cpu.rob.rob_writes                   790440754                       # The number of ROB writes
system.cpu.timesIdled                            6359                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          208714                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   273048466                       # Number of Instructions Simulated
system.cpu.committedOps                     349076190                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             273048466                       # Number of Instructions Simulated
system.cpu.cpi                               0.520959                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.520959                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.919537                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.919537                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1783321389                       # number of integer regfile reads
system.cpu.int_regfile_writes               236147934                       # number of integer regfile writes
system.cpu.fp_regfile_reads                 189806588                       # number of floating regfile reads
system.cpu.fp_regfile_writes                133619756                       # number of floating regfile writes
system.cpu.misc_regfile_reads               991070858                       # number of misc regfile reads
system.cpu.misc_regfile_writes               34426479                       # number of misc regfile writes
system.cpu.icache.replacements                  14002                       # number of replacements
system.cpu.icache.tagsinuse               1857.450296                       # Cycle average of tags in use
system.cpu.icache.total_refs                 39422164                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  15897                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                2479.849280                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1857.450296                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.906958                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.906958                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     39422164                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        39422164                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      39422164                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         39422164                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     39422164                       # number of overall hits
system.cpu.icache.overall_hits::total        39422164                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        17219                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         17219                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        17219                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          17219                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        17219                       # number of overall misses
system.cpu.icache.overall_misses::total         17219                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    362034000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    362034000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    362034000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    362034000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    362034000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    362034000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     39439383                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     39439383                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     39439383                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     39439383                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     39439383                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     39439383                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000437                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000437                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000437                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000437                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000437                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000437                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.262791                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 21025.262791                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.262791                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 21025.262791                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.262791                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 21025.262791                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          660                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                15                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs           44                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1322                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1322                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1322                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1322                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1322                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1322                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15897                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        15897                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        15897                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        15897                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        15897                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        15897                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    295359000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    295359000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    295359000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    295359000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    295359000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    295359000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000403                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000403                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000403                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000403                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000403                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000403                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18579.543310                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18579.543310                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18579.543310                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18579.543310                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18579.543310                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18579.543310                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                   1413                       # number of replacements
system.cpu.dcache.tagsinuse               3122.832455                       # Cycle average of tags in use
system.cpu.dcache.total_refs                172062891                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                   4620                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs               37243.050000                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    3122.832455                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.762410                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.762410                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     90004626                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        90004626                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     82031443                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       82031443                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        13565                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        13565                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        13257                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        13257                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     172036069                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        172036069                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    172036069                       # number of overall hits
system.cpu.dcache.overall_hits::total       172036069                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         4061                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          4061                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        21217                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        21217                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data        25278                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total          25278                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data        25278                       # number of overall misses
system.cpu.dcache.overall_misses::total         25278                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data    164288500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    164288500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    827896681                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    827896681                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       115000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       115000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data    992185181                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total    992185181                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data    992185181                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total    992185181                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     90008687                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     90008687                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     82052660                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052660                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        13567                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        13567                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        13257                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        13257                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    172061347                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    172061347                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    172061347                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    172061347                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000045                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000259                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000259                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000147                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000147                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000147                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000147                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000147                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000147                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40455.183452                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40455.183452                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39020.440260                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 39020.440260                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        57500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        57500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39250.936823                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39250.936823                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39250.936823                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39250.936823                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        13009                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          844                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               400                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              16                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    32.522500                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    52.750000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks         1035                       # number of writebacks
system.cpu.dcache.writebacks::total              1035                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2253                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         2253                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18405                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        18405                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        20658                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        20658                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        20658                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        20658                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1808                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total         1808                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2812                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         2812                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         4620                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4620                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         4620                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4620                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     79609500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total     79609500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131989000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    131989000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    211598500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    211598500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    211598500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    211598500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000034                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44031.803097                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44031.803097                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46937.766714                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46937.766714                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45800.541126                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45800.541126                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45800.541126                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45800.541126                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse              3986.038510                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   13248                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                  5422                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  2.443379                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks   370.679666                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst   2797.931598                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data    817.427246                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.011312                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.085386                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.024946                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.121644                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        12839                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data          301                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          13140                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks         1035                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total         1035                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           17                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           17                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        12839                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data          318                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           13157                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        12839                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data          318                       # number of overall hits
system.cpu.l2cache.overall_hits::total          13157                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3057                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         1506                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4563                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2796                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2796                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3057                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         4302                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          7359                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3057                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         4302                       # number of overall misses
system.cpu.l2cache.overall_misses::total         7359                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    151027000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data     74633000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    225660000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    128994500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    128994500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    151027000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    203627500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    354654500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    151027000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    203627500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    354654500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        15896                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data         1807                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        17703                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks         1035                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total         1035                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         2813                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         2813                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        15896                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         4620                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        20516                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        15896                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         4620                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        20516                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.192313                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.833426                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.257753                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993957                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.993957                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192313                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.931169                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.358696                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192313                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.931169                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.358696                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49403.663723                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49557.104914                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49454.306377                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46135.371960                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46135.371960                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49403.663723                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47333.217108                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 48193.300720                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49403.663723                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47333.217108                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 48193.300720                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           39                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           50                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           39                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           50                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           39                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           50                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3046                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1467                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4513                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2796                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         2796                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3046                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         4263                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         7309                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3046                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         4263                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         7309                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    111924644                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     54839196                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    166763840                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     94353475                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     94353475                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    111924644                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    149192671                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    261117315                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    111924644                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    149192671                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    261117315                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191621                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.811843                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.254929                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993957                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.993957                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191621                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922727                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.356259                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191621                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922727                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.356259                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36744.794485                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37381.865031                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36951.881232                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33745.878040                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33745.878040                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36744.794485                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34997.107905                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35725.450130                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36744.794485                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34997.107905                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35725.450130                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------