path: root/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.124341                       # Number of seconds simulated
sim_ticks                                124340889500                       # Number of ticks simulated
final_tick                               124340889500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 229813                       # Simulator instruction rate (inst/s)
host_op_rate                                   275917                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              104656772                       # Simulator tick rate (ticks/s)
host_mem_usage                                 292960                       # Number of bytes of host memory used
host_seconds                                  1188.08                       # Real time elapsed on the host
sim_insts                                   273037218                       # Number of instructions simulated
sim_ops                                     327811600                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst           1894400                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          14645312                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher       169216                       # Number of bytes read from this memory
system.physmem.bytes_read::total             16708928                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1894400                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1894400                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst              29600                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             228833                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher         2644                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                261077                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst             15235535                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            117783555                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher      1360904                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               134379994                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        15235535                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           15235535                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            15235535                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           117783555                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher      1360904                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              134379994                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        261078                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                      261078                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 16708992                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  16708992                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1259                       # Per bank write bursts
system.physmem.perBankRdBursts::1               69989                       # Per bank write bursts
system.physmem.perBankRdBursts::2                1294                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10805                       # Per bank write bursts
system.physmem.perBankRdBursts::4               42847                       # Per bank write bursts
system.physmem.perBankRdBursts::5              121814                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 160                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 259                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 225                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 562                       # Per bank write bursts
system.physmem.perBankRdBursts::10               7823                       # Per bank write bursts
system.physmem.perBankRdBursts::11                812                       # Per bank write bursts
system.physmem.perBankRdBursts::12               1216                       # Per bank write bursts
system.physmem.perBankRdBursts::13                747                       # Per bank write bursts
system.physmem.perBankRdBursts::14                656                       # Per bank write bursts
system.physmem.perBankRdBursts::15                610                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    124340880000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  261078                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    204158                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     43358                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     12121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       308                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       247                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       209                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       181                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       231                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       123                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        61                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       20                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        67983                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      245.745201                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     180.705876                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     200.483366                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          18259     26.86%     26.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        22263     32.75%     59.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        11383     16.74%     76.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         6868     10.10%     86.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         4760      7.00%     93.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2080      3.06%     96.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1310      1.93%     98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          394      0.58%     99.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          666      0.98%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          67983                       # Bytes accessed per row activation
system.physmem.totQLat                     4612072505                       # Total ticks spent queuing
system.physmem.totMemAccLat                9507285005                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1305390000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       17665.50                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  36415.50                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         134.38                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      134.38                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       1.05                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.60                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                     193085                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   73.96                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       476259.51                       # Average gap between requests
system.physmem.pageHitRate                      73.96                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  450291240                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  239324085                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1773768780                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           9681809280.000002                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy             4644193560                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy              227236800                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       45907805700                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy        3604922400                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy          978458700                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy              67507810545                       # Total energy per rank (pJ)
system.physmem_0.averagePower              542.925264                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           113563299646                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE      155533000                       # Time in different power states
system.physmem_0.memoryStateTime::REF      4097020000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF     3501663750                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN   9387944632                       # Time in different power states
system.physmem_0.memoryStateTime::ACT      6524904104                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 100673824014                       # Time in different power states
system.physmem_1.actEnergy                   35171640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   18667605                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  90321000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3119298000.000000                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy              731861760                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy              127236960                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       10304428080                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy        3803073120                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy        21964091670                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy              40194673995                       # Total energy per rank (pJ)
system.physmem_1.averagePower              323.261913                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           122403387505                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE      207240000                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1323736000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF    89902145500                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN   9903979079                       # Time in different power states
system.physmem_1.memoryStateTime::ACT       406525995                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN  22597262926                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                36038003                       # Number of BP lookups
system.cpu.branchPred.condPredicted          19334387                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            996297                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             17830996                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13933502                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             78.142029                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 6950609                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               4465                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         2515874                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            2470358                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            45516                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       129389                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.numSyscalls                   191                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        248681780                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           13212448                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      309769989                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    36038003                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           23354469                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     231113604                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2018885                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 1934                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            92                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles         3406                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  82291256                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 35072                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          245340926                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.517468                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.300338                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 84879866     34.60%     34.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 40535888     16.52%     51.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 28014472     11.42%     62.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 91910700     37.46%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            245340926                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.144916                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.245648                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 27542743                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              94606230                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  97234991                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              25081957                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 875005                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             12946400                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                134756                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              348426325                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               3406644                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 875005                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 44284460                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                38724844                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         289442                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 104535895                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              56631280                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              344535849                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               1483850                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               7863336                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  96546                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                8390481                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               28393613                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents          3430855                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           394784790                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            2217316444                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        335868704                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         192847846                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             372230048                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 22554742                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              11609                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          11576                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  59430212                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             89918066                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            84391902                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           2366315                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1969070                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  343213178                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               22626                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 339325700                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            951900                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        15424204                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     36793818                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            506                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     245340926                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.383078                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.139070                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            64299867     26.21%     26.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            77319752     31.52%     57.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            59651654     24.31%     82.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            34378652     14.01%     96.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             8900677      3.63%     99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5              777968      0.32%     99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6               12356      0.01%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       245340926                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 8768859      6.80%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   7313      0.01%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMultAcc                 0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMisc                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd            162373      0.13%      6.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.93% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp            163818      0.13%      7.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt             81957      0.06%      7.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv             59658      0.05%      7.17% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc           818593      0.63%      7.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult           313085      0.24%      8.04% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc        382100      0.30%      8.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.34% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               27482783     21.31%     29.65% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              41323323     32.04%     61.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemRead          30643180     23.76%     85.44% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMemWrite         18783688     14.56%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             108181018     31.88%     31.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2148109      0.63%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMultAcc               0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMisc                  0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.51% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         6799471      2.00%     34.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         8597209      2.53%     37.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         3207374      0.95%     38.00% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv         1592649      0.47%     38.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       20858202      6.15%     44.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult        7175067      2.11%     46.73% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc      7140627      2.10%     48.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt         175298      0.05%     48.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             46505269     13.71%     62.59% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            55942906     16.49%     79.08% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemRead        43451689     12.81%     91.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMemWrite       27550812      8.12%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              339325700                       # Type of FU issued
system.cpu.iq.rate                           1.364498                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   128990730                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.380138                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          765966009                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         235211704                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    219112487                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           287968947                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes          123463225                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses    116939299                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              298793937                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses               169522493                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          5585313                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4185791                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         7155                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14925                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2016285                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       158671                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        539433                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 875005                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1351770                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1745589                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           343237205                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              89918066                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             84391902                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              11593                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   6365                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               1739416                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14925                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         447604                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       457294                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               904898                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             337307001                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              89393919                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2018699                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          1401                       # number of nop insts executed
system.cpu.iew.exec_refs                    172494904                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 31547244                       # Number of branches executed
system.cpu.iew.exec_stores                   83100985                       # Number of stores executed
system.cpu.iew.exec_rate                     1.356380                       # Inst execution rate
system.cpu.iew.wb_sent                      336195874                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     336051786                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 153071265                       # num instructions producing a value
system.cpu.iew.wb_consumers                 267284033                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.351333                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.572691                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        14115058                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            861860                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    243135580                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.348269                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.043603                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    113362923     46.63%     46.63% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     66036162     27.16%     73.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     21343595      8.78%     82.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     13169605      5.42%     87.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      8174730      3.36%     91.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      4365960      1.80%     93.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      2981752      1.23%     94.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      2446011      1.01%     95.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     11254842      4.63%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    243135580                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            273037830                       # Number of instructions committed
system.cpu.commit.committedOps              327812212                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      168107892                       # Number of memory references committed
system.cpu.commit.loads                      85732275                       # Number of loads committed
system.cpu.commit.membars                       11033                       # Number of memory barriers committed
system.cpu.commit.branches                   30563525                       # Number of branches committed
system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 258331703                       # Number of committed integer instructions.
system.cpu.commit.function_calls              6225114                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        104312485     31.82%     31.82% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         2145917      0.65%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMultAcc            0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMisc             0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd      6594343      2.01%     34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp      7943502      2.42%     36.91% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt      3118180      0.95%     37.86% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv      1563217      0.48%     38.34% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc     19652356      6.00%     44.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult      7136937      2.18%     46.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc      7062098      2.15%     48.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt       175285      0.05%     48.72% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        44185201     13.48%     62.20% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       55008399     16.78%     78.98% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemRead     41547074     12.67%     91.65% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMemWrite     27367218      8.35%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         327812212                       # Class of committed instruction
system.cpu.commit.bw_lim_events              11254842                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    573805485                       # The number of ROB reads
system.cpu.rob.rob_writes                   686062388                       # The number of ROB writes
system.cpu.timesIdled                           39277                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         3340854                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   273037218                       # Number of Instructions Simulated
system.cpu.committedOps                     327811600                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.910798                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.910798                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.097938                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.097938                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                325088854                       # number of integer regfile reads
system.cpu.int_regfile_writes               134066659                       # number of integer regfile writes
system.cpu.fp_regfile_reads                 186464530                       # number of floating regfile reads
system.cpu.fp_regfile_writes                131741747                       # number of floating regfile writes
system.cpu.cc_regfile_reads                1279144313                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 80001955                       # number of cc regfile writes
system.cpu.misc_regfile_reads              1055862294                       # number of misc regfile reads
system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           1544317                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.844251                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           161914838                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1544829                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            104.810848                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          91273000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.844251                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999696                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999696                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          108                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          307                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           89                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         333130269                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        333130269                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     80902071                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        80902071                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     80921196                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       80921196                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        69698                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         69698                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10906                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10906                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     161823267                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        161823267                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    161892965                       # number of overall hits
system.cpu.dcache.overall_hits::total       161892965                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2746434                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2746434                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1131503                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1131503                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           13                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           13                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      3877937                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3877937                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3877950                       # number of overall misses
system.cpu.dcache.overall_misses::total       3877950                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  47498967000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  47498967000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9188860405                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9188860405                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       194000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       194000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  56687827405                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  56687827405                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  56687827405                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  56687827405                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     83648505                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     83648505                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     82052699                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052699                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data        69711                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total        69711                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10910                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10910                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    165701204                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    165701204                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    165770915                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    165770915                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032833                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.032833                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013790                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.013790                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000186                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.000186                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000367                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000367                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.023403                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.023403                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.023393                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.023393                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17294.778247                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17294.778247                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8120.933312                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  8120.933312                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        48500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        48500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14618.037221                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14618.037221                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.988217                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14617.988217                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      1101938                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          136754                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     8.057812                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      1544317                       # number of writebacks
system.cpu.dcache.writebacks::total           1544317                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1422290                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1422290                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       910806                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       910806                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2333096                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2333096                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2333096                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2333096                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1324144                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1324144                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220697                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       220697                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            7                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total            7                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1544841                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1544841                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1544848                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1544848                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  27090401500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  27090401500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1844259187                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   1844259187                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       932500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       932500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28934660687                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  28934660687                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28935593187                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  28935593187                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015830                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015830                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002690                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002690                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000100                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000100                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009323                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.009323                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009319                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.009319                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20458.803197                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20458.803197                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8356.521326                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8356.521326                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 133214.285714                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 133214.285714                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18729.863259                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18729.863259                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18730.382010                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18730.382010                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements            727442                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.812488                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            81555981                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            727954                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            112.034526                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle         348938500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.812488                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999634                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999634                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          162                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           98                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           67                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         165310431                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        165310431                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     81555981                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        81555981                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      81555981                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         81555981                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     81555981                       # number of overall hits
system.cpu.icache.overall_hits::total        81555981                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       735249                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        735249                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       735249                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         735249                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       735249                       # number of overall misses
system.cpu.icache.overall_misses::total        735249                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   8470113937                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   8470113937                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   8470113937                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   8470113937                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   8470113937                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   8470113937                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     82291230                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     82291230                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     82291230                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     82291230                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     82291230                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     82291230                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008935                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.008935                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.008935                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.008935                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.008935                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.008935                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11520.061825                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 11520.061825                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 11520.061825                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 11520.061825                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 11520.061825                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 11520.061825                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       144128                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          153                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              4365                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    33.019015                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           51                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks       727442                       # number of writebacks
system.cpu.icache.writebacks::total            727442                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7277                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         7277                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         7277                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         7277                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         7277                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         7277                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       727972                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       727972                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       727972                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       727972                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       727972                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       727972                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   7937418446                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   7937418446                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   7937418446                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   7937418446                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   7937418446                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   7937418446                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008846                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008846                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008846                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.008846                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008846                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.008846                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10903.466680                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10903.466680                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10903.466680                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 10903.466680                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10903.466680                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 10903.466680                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued       402290                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified       402345                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit           51                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage        28015                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         5251.876732                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1819467                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             6313                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs           288.209568                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  5160.149937                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    91.726796                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.314951                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.005599                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.320549                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          185                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         6128                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0           12                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           48                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3            2                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4          101                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          161                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          547                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          740                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          550                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4130                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.011292                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.374023                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         70659625                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        70659625                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks       968794                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       968794                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      1048519                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      1048519                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       219908                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       219908                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       698283                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       698283                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1095997                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1095997                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst       698283                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1315905                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2014188                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       698283                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1315905                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2014188                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           18                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           18                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data          790                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          790                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        29612                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        29612                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       228134                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       228134                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        29612                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       228924                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        258536                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        29612                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       228924                       # number of overall misses
system.cpu.l2cache.overall_misses::total       258536                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        43000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        43000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     70196000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     70196000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2658292500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2658292500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17944343500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  17944343500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2658292500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  18014539500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  20672832000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2658292500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  18014539500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  20672832000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       968794                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       968794                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      1048519                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      1048519                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           19                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           19                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       220698                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       220698                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       727895                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       727895                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1324131                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1324131                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       727895                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1544829                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2272724                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       727895                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1544829                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2272724                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.947368                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.947368                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003580                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.003580                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.040682                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.040682                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.172290                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.172290                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.040682                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.148187                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.113756                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.040682                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.148187                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.113756                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  2388.888889                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  2388.888889                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88855.696203                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88855.696203                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89770.785492                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89770.785492                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78657.032709                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78657.032709                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89770.785492                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78692.227552                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79961.135006                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89770.785492                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78692.227552                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79961.135006                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           55                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total           55                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           11                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           11                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           36                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           36                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           91                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total          102                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           91                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total          102                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        54077                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total        54077                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           18                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           18                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          735                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          735                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        29601                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        29601                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       228098                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       228098                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        29601                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       228833                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       258434                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        29601                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       228833                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        54077                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       312511                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    203156315                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    203156315                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       279000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       279000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     64169000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     64169000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2480103000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2480103000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16573484500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16573484500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2480103000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  16637653500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  19117756500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2480103000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  16637653500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    203156315                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  19320912815                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.947368                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.947368                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003330                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003330                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.040667                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040667                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.172262                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.172262                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.040667                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148128                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.113711                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.040667                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148128                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.137505                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3756.797067                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3756.797067                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        15500                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        15500                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87304.761905                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87304.761905                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83784.432958                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83784.432958                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72659.490658                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72659.490658                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83784.432958                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72706.530527                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73975.392170                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83784.432958                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72706.530527                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3756.797067                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61824.744777                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      4544579                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2271779                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests       254895                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops        51433                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops        51432                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       2052102                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       968794                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      1302965                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq        55467                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           19                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           19                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       220698                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       220698                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       727972                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1324131                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2183308                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4634013                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           6817321                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     93141504                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    197705344                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          290846848                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       55544                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                  4928                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      2328287                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.131576                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.338031                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2021941     86.84%     86.84% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             306345     13.16%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2328287                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4544048500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          3.7                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1092026360                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2317274956                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.9                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests        261096                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       253777                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 124340889500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp             260342                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               18                       # Transaction distribution
system.membus.trans_dist::ReadExReq               735                       # Transaction distribution
system.membus.trans_dist::ReadExResp              735                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        260343                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       522173                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 522173                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16708928                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                16708928                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            261096                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  261096    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              261096                       # Request fanout histogram
system.membus.reqLayer0.occupancy           316188421                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1389693354                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------