path: root/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.120480                       # Number of seconds simulated
sim_ticks                                120480458500                       # Number of ticks simulated
final_tick                               120480458500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 129515                       # Simulator instruction rate (inst/s)
host_op_rate                                   155497                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               57149813                       # Simulator tick rate (ticks/s)
host_mem_usage                                 293332                       # Number of bytes of host memory used
host_seconds                                  2108.15                       # Real time elapsed on the host
sim_insts                                   273037218                       # Number of instructions simulated
sim_ops                                     327811600                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst           1888064                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          14651392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher       167808                       # Number of bytes read from this memory
system.physmem.bytes_read::total             16707264                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      1888064                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1888064                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst              29501                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             228928                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher         2622                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                261051                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst             15671122                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            121608037                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher      1392823                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               138671982                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        15671122                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           15671122                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            15671122                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           121608037                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher      1392823                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              138671982                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        261052                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                      261052                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 16707328                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  16707328                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1258                       # Per bank write bursts
system.physmem.perBankRdBursts::1               69992                       # Per bank write bursts
system.physmem.perBankRdBursts::2                1296                       # Per bank write bursts
system.physmem.perBankRdBursts::3               10757                       # Per bank write bursts
system.physmem.perBankRdBursts::4               42908                       # Per bank write bursts
system.physmem.perBankRdBursts::5              121820                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 160                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 266                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 224                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 562                       # Per bank write bursts
system.physmem.perBankRdBursts::10               7776                       # Per bank write bursts
system.physmem.perBankRdBursts::11                812                       # Per bank write bursts
system.physmem.perBankRdBursts::12               1213                       # Per bank write bursts
system.physmem.perBankRdBursts::13                743                       # Per bank write bursts
system.physmem.perBankRdBursts::14                656                       # Per bank write bursts
system.physmem.perBankRdBursts::15                609                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    120480449000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  261052                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    204297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     43283                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     12075                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       298                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       208                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       182                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       216                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       113                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        58                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                       21                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                       18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                       18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        67045                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      249.160415                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     181.717328                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     205.520754                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          18369     27.40%     27.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        21159     31.56%     58.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        11457     17.09%     76.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         6629      9.89%     85.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         4618      6.89%     92.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2220      3.31%     96.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1372      2.05%     98.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          491      0.73%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151          730      1.09%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          67045                       # Bytes accessed per row activation
system.physmem.totQLat                     2500931533                       # Total ticks spent queuing
system.physmem.totMemAccLat                7395656533                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1305260000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9580.20                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28330.20                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         138.67                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      138.67                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.08                       # Data bus utilization in percentage
system.physmem.busUtilRead                       1.08                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.60                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                     193998                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.31                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                       461518.97                       # Average gap between requests
system.physmem.pageHitRate                      74.31                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  469687680                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  256278000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1937777400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             7868948880                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            73664414550                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             7668236250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              91865342760                       # Total energy per rank (pJ)
system.physmem_0.averagePower              762.514125                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    12350213739                       # Time in different power states
system.physmem_0.memoryStateTime::REF      4022980000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    104104852261                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                   37134720                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                   20262000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  98069400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             7868948880                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            16939770435                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            57426696000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              82390881435                       # Total energy per rank (pJ)
system.physmem_1.averagePower              683.872818                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    95444315624                       # Time in different power states
system.physmem_1.memoryStateTime::REF      4022980000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     21009739880                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups                35971487                       # Number of BP lookups
system.cpu.branchPred.condPredicted          19266966                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            984300                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             17894295                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                13923321                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             77.808715                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 6951891                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               4417                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups         2517210                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits            2473355                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            43855                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted       128902                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        240960918                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           12852393                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      309387545                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    35971487                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           23348567                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     224289895                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1990323                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 1871                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            93                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles         3026                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  82204082                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 34266                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          238142439                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.562665                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.293284                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 77933727     32.73%     32.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 40203358     16.88%     49.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 28082672     11.79%     61.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 91922682     38.60%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            238142439                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.149283                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.283974                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 26809492                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              87975457                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  98235303                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              24260898                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 861289                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              6686645                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                134215                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              348536073                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               3411178                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 861289                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 43087679                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                34729777                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         287359                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 105264108                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              53912227                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              344595535                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               1451317                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               7117459                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  85486                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                7456793                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               27429966                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents          3277218                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           394867605                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            2218081796                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        335910446                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         192911530                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             372230048                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 22637557                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              11606                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          11573                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  57394706                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             89984018                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            84392471                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1976841                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1898355                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  343274386                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               22623                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 339465004                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            967637                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        15485409                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     37250778                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            503                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     238142439                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.425470                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.136916                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            57979720     24.35%     24.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            76155774     31.98%     56.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            59457503     24.97%     81.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            34550396     14.51%     95.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             9286722      3.90%     99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5              677796      0.28%     99.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6               34528      0.01%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       238142439                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 9217758      7.75%      7.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   7319      0.01%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.76% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd            238781      0.20%      7.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.96% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp            138932      0.12%      8.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt             70694      0.06%      8.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv             68373      0.06%      8.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc           637081      0.54%      8.73% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult           296736      0.25%      8.98% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc        541785      0.46%      9.43% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.43% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               51510154     43.32%     52.75% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              56187310     47.25%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             108183295     31.87%     31.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2148337      0.63%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         6792696      2.00%     34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         8634939      2.54%     37.05% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         3210556      0.95%     37.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv         1592986      0.47%     38.46% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       20863290      6.15%     44.61% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult        7179112      2.11%     46.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc      7141893      2.10%     48.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt         175297      0.05%     48.88% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             90024001     26.52%     75.40% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            83518602     24.60%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              339465004                       # Type of FU issued
system.cpu.iq.rate                           1.408797                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   118914923                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.350301                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          753593457                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         235149136                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    219170609                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           283361550                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes          123645361                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses    116917491                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              293630516                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses               164749411                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          5409371                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      4251743                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         7382                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        12082                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2016854                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       126951                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        613385                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 861289                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1346418                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1223561                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           343298428                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              89984018                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             84392471                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              11590                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   7654                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               1216581                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          12082                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         438027                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       454511                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               892538                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             337435973                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              89435470                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           2029031                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          1419                       # number of nop insts executed
system.cpu.iew.exec_refs                    172563167                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 31555788                       # Number of branches executed
system.cpu.iew.exec_stores                   83127697                       # Number of stores executed
system.cpu.iew.exec_rate                     1.400376                       # Inst execution rate
system.cpu.iew.wb_sent                      336234414                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     336088100                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 151781597                       # num instructions producing a value
system.cpu.iew.wb_consumers                 263546089                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.394783                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.575921                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        14163176                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            850428                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    235953046                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.389311                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.042233                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    104793604     44.41%     44.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     67594704     28.65%     73.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     20883417      8.85%     81.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     13239055      5.61%     87.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      8655759      3.67%     91.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      4517031      1.91%     93.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      3019754      1.28%     94.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      2590982      1.10%     95.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     10658740      4.52%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    235953046                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            273037830                       # Number of instructions committed
system.cpu.commit.committedOps              327812212                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      168107892                       # Number of memory references committed
system.cpu.commit.loads                      85732275                       # Number of loads committed
system.cpu.commit.membars                       11033                       # Number of memory barriers committed
system.cpu.commit.branches                   30563525                       # Number of branches committed
system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 258331703                       # Number of committed integer instructions.
system.cpu.commit.function_calls              6225114                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        104312485     31.82%     31.82% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         2145917      0.65%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd      6594343      2.01%     34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp      7943502      2.42%     36.91% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt      3118180      0.95%     37.86% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv      1563217      0.48%     38.34% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc     19652356      6.00%     44.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult      7136937      2.18%     46.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc      7062098      2.15%     48.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt       175285      0.05%     48.72% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        85732275     26.15%     74.87% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       82375617     25.13%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         327812212                       # Class of committed instruction
system.cpu.commit.bw_lim_events              10658740                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    567267171                       # The number of ROB reads
system.cpu.rob.rob_writes                   686142351                       # The number of ROB writes
system.cpu.timesIdled                           39413                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         2818479                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   273037218                       # Number of Instructions Simulated
system.cpu.committedOps                     327811600                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.882520                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.882520                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.133118                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.133118                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                325162337                       # number of integer regfile reads
system.cpu.int_regfile_writes               134093699                       # number of integer regfile writes
system.cpu.fp_regfile_reads                 186638060                       # number of floating regfile reads
system.cpu.fp_regfile_writes                131662989                       # number of floating regfile writes
system.cpu.cc_regfile_reads                1279404689                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 80058303                       # number of cc regfile writes
system.cpu.misc_regfile_reads              1056730531                       # number of misc regfile reads
system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           1542807                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.846983                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           162052499                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1543319                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            105.002594                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle          87321000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.846983                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999701                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999701                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          308                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         333478959                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        333478959                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data     81039652                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        81039652                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     80921351                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       80921351                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        69633                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         69633                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10908                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10908                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     161961003                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        161961003                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    162030636                       # number of overall hits
system.cpu.dcache.overall_hits::total       162030636                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2784011                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2784011                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1131348                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1131348                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data           18                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           18                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      3915359                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3915359                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3915377                       # number of overall misses
system.cpu.dcache.overall_misses::total       3915377                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  45256653500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  45256653500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9138834402                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9138834402                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       184000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       184000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  54395487902                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  54395487902                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  54395487902                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  54395487902                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     83823663                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     83823663                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     82052699                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052699                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data        69651                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total        69651                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10912                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10912                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    165876362                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    165876362                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    165946013                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    165946013                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033213                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.033213                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013788                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.013788                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000258                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.000258                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000367                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000367                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.023604                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.023604                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.023594                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.023594                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16255.917631                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16255.917631                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8077.827867                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  8077.827867                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        46000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        46000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13892.848115                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 13892.848115                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13892.784246                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 13892.784246                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      1086145                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          136219                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     7.973521                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      1542807                       # number of writebacks
system.cpu.dcache.writebacks::total           1542807                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1461430                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1461430                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       910604                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       910604                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2372034                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2372034                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2372034                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2372034                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1322581                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1322581                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220744                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       220744                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           11                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           11                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1543325                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1543325                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1543336                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1543336                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  25407816000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  25407816000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1834277181                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   1834277181                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       705000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       705000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27242093181                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  27242093181                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27242798181                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  27242798181                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015778                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015778                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002690                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002690                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000158                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000158                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009304                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.009304                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009300                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.009300                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19210.782553                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19210.782553                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8309.522257                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8309.522257                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64090.909091                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64090.909091                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17651.559575                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17651.559575                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17651.890568                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17651.890568                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements            725593                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.815316                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            81471161                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            726105                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            112.203002                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle         334835500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.815316                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999639                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999639                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          243                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           70                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         165134244                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        165134244                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst     81471161                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        81471161                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      81471161                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         81471161                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     81471161                       # number of overall hits
system.cpu.icache.overall_hits::total        81471161                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       732901                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        732901                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       732901                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         732901                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       732901                       # number of overall misses
system.cpu.icache.overall_misses::total        732901                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   8031652441                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   8031652441                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   8031652441                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   8031652441                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   8031652441                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   8031652441                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     82204062                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     82204062                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     82204062                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     82204062                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     82204062                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     82204062                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008916                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.008916                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.008916                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.008916                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.008916                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.008916                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10958.713989                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 10958.713989                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 10958.713989                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 10958.713989                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 10958.713989                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 10958.713989                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       128534                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          100                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              4274                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    30.073467                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    33.333333                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks       725593                       # number of writebacks
system.cpu.icache.writebacks::total            725593                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         6780                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         6780                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         6780                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         6780                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         6780                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         6780                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       726121                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       726121                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       726121                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       726121                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       726121                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       726121                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   7527879949                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   7527879949                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   7527879949                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   7527879949                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   7527879949                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   7527879949                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008833                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008833                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008833                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.008833                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008833                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.008833                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10367.252771                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10367.252771                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10367.252771                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 10367.252771                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10367.252771                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 10367.252771                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued       402848                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified       402975                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit          113                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage        27937                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         5253.562311                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1811987                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             6314                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs           286.979252                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  5154.206528                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    99.355783                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.314588                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006064                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.320652                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          192                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         6122                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0           12                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           48                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4          110                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          555                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1137                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          139                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4125                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.011719                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.373657                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         70548606                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        70548606                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks       968253                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       968253                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      1045699                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      1045699                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       219932                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       219932                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       696525                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       696525                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1094373                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1094373                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst       696525                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1314305                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2010830                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       696525                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1314305                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2010830                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           16                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           16                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data          807                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          807                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        29515                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        29515                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       228207                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       228207                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst        29515                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       229014                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        258529                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst        29515                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       229014                       # number of overall misses
system.cpu.l2cache.overall_misses::total       258529                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        43000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        43000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     59970500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     59970500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   2262045500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   2262045500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  16271473000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  16271473000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   2262045500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  16331443500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  18593489000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   2262045500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  16331443500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  18593489000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       968253                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       968253                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      1045699                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      1045699                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       220739                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       220739                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       726040                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       726040                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1322580                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      1322580                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       726040                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1543319                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2269359                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       726040                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1543319                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2269359                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.941176                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.941176                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003656                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.003656                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.040652                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.040652                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.172547                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.172547                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.040652                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.148391                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.113922                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.040652                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.148391                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.113922                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  2687.500000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  2687.500000                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74312.887237                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74312.887237                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76640.538709                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76640.538709                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 71301.375506                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 71301.375506                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76640.538709                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71311.987477                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71920.322285                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76640.538709                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71311.987477                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71920.322285                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           50                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total           50                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           36                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           36                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           13                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           86                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           99                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           13                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           86                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           99                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        54157                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total        54157                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          757                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          757                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        29502                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        29502                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       228171                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       228171                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        29502                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       228928                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       258430                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        29502                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       228928                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        54157                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       312587                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    187753381                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    187753381                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       251000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       251000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     53315000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     53315000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   2084473500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   2084473500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  14900259000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  14900259000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   2084473500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  14953574000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  17038047500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   2084473500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  14953574000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    187753381                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  17225800881                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.941176                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.941176                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003429                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003429                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.040634                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.040634                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.172520                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.172520                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.040634                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148335                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.113878                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.040634                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148335                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.137742                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3466.834961                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3466.834961                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15687.500000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15687.500000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70429.326288                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70429.326288                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70655.328452                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70655.328452                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65303.035881                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65303.035881                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70655.328452                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65319.987070                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65929.062028                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70655.328452                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65319.987070                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3466.834961                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55107.220969                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      4537857                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      2268434                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests       254467                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops        51535                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops        51534                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       2048700                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       968253                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      1300147                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq        55525                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       220739                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       220739                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       726121                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      1322580                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2177753                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4629479                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           6807232                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     92904448                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    197512064                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          290416512                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       55606                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic                  5184                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      2324982                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.131629                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.338088                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            2018948     86.84%     86.84% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             306033     13.16%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        2324982                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     4537328500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          3.8                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    1089458442                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2315007958                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.9                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests        261068                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       253748                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 120480458500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp             260294                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
system.membus.trans_dist::ReadExReq               757                       # Transaction distribution
system.membus.trans_dist::ReadExResp              757                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        260295                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       522119                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 522119                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16707264                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                16707264                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            261068                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  261068    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              261068                       # Request fanout histogram
system.membus.reqLayer0.occupancy           329929457                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1377865586                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------