1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.112554 # Number of seconds simulated
sim_ticks 112553814500 # Number of ticks simulated
final_tick 112553814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 125235 # Simulator instruction rate (inst/s)
host_op_rate 150358 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 51625290 # Simulator tick rate (ticks/s)
host_mem_usage 326264 # Number of bytes of host memory used
host_seconds 2180.21 # Real time elapsed on the host
sim_insts 273037219 # Number of instructions simulated
sim_ops 327811601 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 187136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 114176 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 167616 # Number of bytes read from this memory
system.physmem.bytes_read::total 468928 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 187136 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 187136 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2924 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1784 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 2619 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7327 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1662636 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1014413 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 1489208 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4166256 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1662636 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1662636 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1662636 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1014413 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 1489208 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4166256 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7327 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7327 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 468928 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 468928 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 589 # Per bank write bursts
system.physmem.perBankRdBursts::1 789 # Per bank write bursts
system.physmem.perBankRdBursts::2 601 # Per bank write bursts
system.physmem.perBankRdBursts::3 520 # Per bank write bursts
system.physmem.perBankRdBursts::4 444 # Per bank write bursts
system.physmem.perBankRdBursts::5 346 # Per bank write bursts
system.physmem.perBankRdBursts::6 153 # Per bank write bursts
system.physmem.perBankRdBursts::7 255 # Per bank write bursts
system.physmem.perBankRdBursts::8 219 # Per bank write bursts
system.physmem.perBankRdBursts::9 290 # Per bank write bursts
system.physmem.perBankRdBursts::10 315 # Per bank write bursts
system.physmem.perBankRdBursts::11 411 # Per bank write bursts
system.physmem.perBankRdBursts::12 547 # Per bank write bursts
system.physmem.perBankRdBursts::13 678 # Per bank write bursts
system.physmem.perBankRdBursts::14 615 # Per bank write bursts
system.physmem.perBankRdBursts::15 555 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 112553656000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 7327 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 3994 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 473 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 246 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 203 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 150 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 184 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1397 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 334.064424 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 193.482672 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 348.087808 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 504 36.08% 36.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 315 22.55% 58.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 145 10.38% 69.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 78 5.58% 74.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 51 3.65% 78.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 45 3.22% 81.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 28 2.00% 83.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 21 1.50% 84.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 210 15.03% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1397 # Bytes accessed per row activation
system.physmem.totQLat 96387273 # Total ticks spent queuing
system.physmem.totMemAccLat 233768523 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 36635000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13155.08 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 31905.08 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 5921 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 15361492.56 # Average gap between requests
system.physmem.pageHitRate 80.81 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 3253381020 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 64676459250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 75317311980 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.186805 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 107592163396 # Time in different power states
system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1200480604 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 28158000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 3298234320 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 64637123250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 75323490750 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.241613 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 107525247142 # Time in different power states
system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1266984612 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 37745757 # Number of BP lookups
system.cpu.branchPred.condPredicted 20165080 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1746215 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 18666199 # Number of BTB lookups
system.cpu.branchPred.BTBHits 17299874 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 92.680218 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 7225607 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 225107630 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 12251626 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 334050460 # Number of instructions fetch has processed
system.cpu.fetch.Branches 37745757 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 24525481 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 210773788 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3510701 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1259 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 2425 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 89095014 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 21830 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 224784448 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.802641 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.228554 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 51100209 22.73% 22.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 42897495 19.08% 41.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 30052167 13.37% 55.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 100734577 44.81% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 224784448 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.167679 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.483959 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 27670459 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 63847459 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 108576617 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 23069322 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1620591 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 6880031 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 363530052 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 6167703 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 1620591 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 44985233 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 17899875 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 341878 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 113387886 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 46548985 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 355747640 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 2899285 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 6598470 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 195112 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7751940 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 21223571 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 2892429 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 403401871 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2533892950 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 350207607 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 194891234 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 31171820 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 55320329 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 92416671 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 88482299 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1659115 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1844729 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 353235129 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 346404668 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 2300304 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 24831082 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 73599170 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 224784448 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.541053 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.099675 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 40431348 17.99% 17.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 78272117 34.82% 52.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 61035980 27.15% 79.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 34788778 15.48% 95.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 9595638 4.27% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 651817 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 8770 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 224784448 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 9471276 7.62% 7.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 7330 0.01% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 257049 0.21% 7.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 126990 0.10% 7.94% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 92940 0.07% 8.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 68000 0.05% 8.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 719474 0.58% 8.64% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 316340 0.25% 8.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 682824 0.55% 9.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 53604156 43.13% 52.57% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 58946138 47.43% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 110656025 31.94% 31.94% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2148357 0.62% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 6798490 1.96% 34.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 8668315 2.50% 37.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 3332477 0.96% 37.99% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1592461 0.46% 38.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 20930112 6.04% 44.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 7182294 2.07% 46.57% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148952 2.06% 48.63% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 91886799 26.53% 75.21% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 85885100 24.79% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 346404668 # Type of FU issued
system.cpu.iq.rate 1.538840 # Inst issue rate
system.cpu.iq.fu_busy_cnt 124292517 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.358807 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 756686876 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 251306416 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 223263085 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 287499729 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 126798006 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 117424806 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 303164482 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 167532703 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5066223 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 6684396 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13685 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 10191 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6106682 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 154303 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 567640 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1620591 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 2121620 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 330440 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 353264020 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 92416671 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 88482299 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 8046 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 336925 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 10191 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1220622 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 439103 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1659725 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 342414286 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 90666955 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3990382 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 867 # number of nop insts executed
system.cpu.iew.exec_refs 175255989 # number of memory reference insts executed
system.cpu.iew.exec_branches 31752931 # Number of branches executed
system.cpu.iew.exec_stores 84589034 # Number of stores executed
system.cpu.iew.exec_rate 1.521114 # Inst execution rate
system.cpu.iew.wb_sent 340946352 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 340687891 # cumulative count of insts written-back
system.cpu.iew.wb_producers 153731206 # num instructions producing a value
system.cpu.iew.wb_consumers 266896125 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.513444 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.575996 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 23077118 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1611456 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 221059297 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.482915 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.052167 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 87356112 39.52% 39.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 70369552 31.83% 71.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 20804455 9.41% 80.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 13442204 6.08% 86.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8808979 3.98% 90.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 4514912 2.04% 92.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2991653 1.35% 94.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 2424695 1.10% 95.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 10346735 4.68% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 221059297 # Number of insts commited each cycle
system.cpu.commit.committedInsts 273037831 # Number of instructions committed
system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 168107892 # Number of memory references committed
system.cpu.commit.loads 85732275 # Number of loads committed
system.cpu.commit.membars 11033 # Number of memory barriers committed
system.cpu.commit.branches 30563525 # Number of branches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.int_insts 258331704 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225114 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 104312486 31.82% 31.82% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 85732275 26.15% 74.87% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction
system.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 561599370 # The number of ROB reads
system.cpu.rob.rob_writes 705507733 # The number of ROB writes
system.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 323182 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273037219 # Number of Instructions Simulated
system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.824458 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.824458 # CPI: Total CPI of All Threads
system.cpu.ipc 1.212919 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.212919 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 331300708 # number of integer regfile reads
system.cpu.int_regfile_writes 136940215 # number of integer regfile writes
system.cpu.fp_regfile_reads 187107289 # number of floating regfile reads
system.cpu.fp_regfile_writes 132177847 # number of floating regfile writes
system.cpu.cc_regfile_reads 1297030245 # number of cc regfile reads
system.cpu.cc_regfile_writes 80242169 # number of cc regfile writes
system.cpu.misc_regfile_reads 1182847920 # number of misc regfile reads
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
system.cpu.dcache.tags.replacements 1533856 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.843197 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 163689216 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 106.681849 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 83394000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.843197 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 336633502 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 336633502 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 82631348 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 82631348 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 80965582 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 80965582 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 70480 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 70480 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 163596930 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 163596930 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 163667410 # number of overall hits
system.cpu.dcache.overall_hits::total 163667410 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2773213 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2773213 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1087117 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1087117 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 3860330 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3860330 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3860348 # number of overall misses
system.cpu.dcache.overall_misses::total 3860348 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 22349106216 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 22349106216 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8902471046 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8902471046 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 31251577262 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 31251577262 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 31251577262 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 31251577262 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 85404561 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 85404561 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 70498 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 70498 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 167457260 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 167457260 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 167527758 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 167527758 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.032471 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8058.921625 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 8058.921625 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8189.064329 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 8189.064329 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 8095.571431 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 8095.571431 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 8095.533683 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 8095.533683 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 918314 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 117385 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 7.823095 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks
system.cpu.dcache.writebacks::total 966341 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459499 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1459499 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866472 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 866472 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2325971 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2325971 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2325971 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2325971 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9969290033 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9969290033 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717345064 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717345064 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1161750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1161750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686635097 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11686635097 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11687796847 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11687796847 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7588.630427 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7588.630427 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7783.294722 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7783.294722 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 105613.636364 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 105613.636364 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7616.623683 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 7616.623683 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7617.326230 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 7617.326230 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 715719 # number of replacements
system.cpu.icache.tags.tagsinuse 511.828705 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 88373879 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 716231 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 123.387397 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 326261250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.828705 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999665 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999665 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 178906226 # Number of tag accesses
system.cpu.icache.tags.data_accesses 178906226 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 88373879 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 88373879 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 88373879 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 88373879 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 88373879 # number of overall hits
system.cpu.icache.overall_hits::total 88373879 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 721118 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 721118 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 721118 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 721118 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 721118 # number of overall misses
system.cpu.icache.overall_misses::total 721118 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 5972962690 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 5972962690 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 5972962690 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 5972962690 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 5972962690 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 5972962690 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 89094997 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 89094997 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 89094997 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 89094997 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 89094997 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 89094997 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8282.919980 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 8282.919980 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 8282.919980 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 8282.919980 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 60262 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2026 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 29.744324 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716232 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 716232 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 716232 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 716232 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 716232 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 716232 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5192936459 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 5192936459 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5192936459 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 5192936459 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5192936459 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 5192936459 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7250.355275 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7250.355275 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued 404550 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 404804 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 188 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 28140 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 5993.813794 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2806615 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 7301 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 384.415149 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 2575.149913 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2681.614006 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 610.589138 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 126.460737 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.157175 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163673 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.037267 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007719 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.365833 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 517 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 6784 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 135 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 775 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 126 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5743 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031555 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414062 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 51684538 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 51684538 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 712391 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1312672 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2025063 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 966341 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 966341 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 219831 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 219831 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 712391 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1532503 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2244894 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 712391 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1532503 # number of overall hits
system.cpu.l2cache.overall_hits::total 2244894 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 2935 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1053 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 3988 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 812 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 812 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2935 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1865 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 4800 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2935 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1865 # number of overall misses
system.cpu.l2cache.overall_misses::total 4800 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200800474 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76846248 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 277646722 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57691250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 57691250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 200800474 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 134537498 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 335337972 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 200800474 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 134537498 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 335337972 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 715326 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1313725 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2029051 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 966341 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 966341 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 220643 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 220643 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 715326 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1534368 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2249694 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 715326 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1534368 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2249694 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004103 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000802 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001965 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003680 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.003680 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004103 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.001215 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.002134 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004103 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.001215 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.002134 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68415.834412 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72978.393162 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69620.542126 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23499 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23499 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71048.337438 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71048.337438 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69862.077500 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69862.077500 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 47 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 47 # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 92 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2924 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1019 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 3943 # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30395 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 30395 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 765 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 765 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2924 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1784 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 4708 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2924 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1784 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30395 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 35103 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175338026 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 66096002 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 241434028 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 176500042 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14001 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14001 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49863251 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49863251 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175338026 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115959253 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 291297279 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175338026 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115959253 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 467797321 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000776 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001943 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003467 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003467 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.002093 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.015603 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59965.125171 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64863.593719 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61231.049455 # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5806.877513 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65180.720261 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65180.720261 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61872.829014 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13326.419993 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2029957 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2029957 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 31800 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431558 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 5466639 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780864 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 205826240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 32706 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3248743 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3.009788 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.098451 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 3216943 99.02% 99.02% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 31800 0.98% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3248743 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2574812500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1075185997 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2301792968 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 6562 # Transaction distribution
system.membus.trans_dist::ReadResp 6562 # Transaction distribution
system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 765 # Transaction distribution
system.membus.trans_dist::ReadExResp 765 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468928 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 468928 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 7328 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 7328 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7328 # Request fanout histogram
system.membus.reqLayer0.occupancy 9247379 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 38369962 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
|