path: root/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.068504                       # Number of seconds simulated
sim_ticks                                 68503867000                       # Number of ticks simulated
final_tick                                68503867000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 147835                       # Simulator instruction rate (inst/s)
host_op_rate                                   189000                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               37091215                       # Simulator tick rate (ticks/s)
host_mem_usage                                 278164                       # Number of bytes of host memory used
host_seconds                                  1846.90                       # Real time elapsed on the host
sim_insts                                   273036725                       # Number of instructions simulated
sim_ops                                     349064449                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            193984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            272256                       # Number of bytes read from this memory
system.physmem.bytes_read::total               466240                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       193984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          193984                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               3031                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               4254                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                  7285                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              2831723                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              3974316                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 6806039                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         2831723                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            2831723                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             2831723                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             3974316                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                6806039                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                          7286                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                        7286                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   466304                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    466304                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              2                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                 606                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 800                       # Per bank write bursts
system.physmem.perBankRdBursts::2                 608                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 526                       # Per bank write bursts
system.physmem.perBankRdBursts::4                 443                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 354                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 164                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 219                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 207                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 291                       # Per bank write bursts
system.physmem.perBankRdBursts::10                322                       # Per bank write bursts
system.physmem.perBankRdBursts::11                415                       # Per bank write bursts
system.physmem.perBankRdBursts::12                529                       # Per bank write bursts
system.physmem.perBankRdBursts::13                687                       # Per bank write bursts
system.physmem.perBankRdBursts::14                611                       # Per bank write bursts
system.physmem.perBankRdBursts::15                504                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     68503846500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                    7286                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                      4373                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                      2103                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       567                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       176                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        66                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         1286                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      361.604977                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     163.647663                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     753.981601                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65            537     41.76%     41.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129          220     17.11%     58.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193          131     10.19%     69.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257           77      5.99%     75.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321           39      3.03%     78.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385           38      2.95%     81.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449           26      2.02%     83.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513           31      2.41%     85.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577           17      1.32%     86.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641           23      1.79%     88.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705            6      0.47%     89.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769           16      1.24%     90.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833            3      0.23%     90.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897            8      0.62%     91.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961            7      0.54%     91.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025            7      0.54%     92.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089            5      0.39%     92.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153            8      0.62%     93.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217            5      0.39%     93.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281            6      0.47%     94.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345            1      0.08%     94.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409            4      0.31%     94.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473            4      0.31%     94.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537            6      0.47%     95.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601            3      0.23%     95.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665            3      0.23%     95.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729            3      0.23%     95.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793            4      0.31%     96.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921            2      0.16%     96.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985            3      0.23%     96.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049            2      0.16%     96.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113            4      0.31%     97.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177            2      0.16%     97.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241            1      0.08%     97.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305            1      0.08%     97.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369            2      0.16%     97.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497            1      0.08%     97.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561            1      0.08%     97.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625            1      0.08%     97.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753            1      0.08%     97.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817            1      0.08%     97.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881            2      0.16%     98.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945            1      0.08%     98.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009            2      0.16%     98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073            1      0.08%     98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137            1      0.08%     98.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201            1      0.08%     98.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329            1      0.08%     98.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585            2      0.16%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713            1      0.08%     98.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841            1      0.08%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033            1      0.08%     99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097            1      0.08%     99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161            1      0.08%     99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609            3      0.23%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737            1      0.08%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465            1      0.08%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529            1      0.08%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657            1      0.08%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553            1      0.08%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193            2      0.16%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           1286                       # Bytes accessed per row activation
system.physmem.totQLat                       62980000                       # Total ticks spent queuing
system.physmem.totMemAccLat                 198080000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     36430000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                    98670000                       # Total ticks spent accessing banks
system.physmem.avgQLat                        8643.97                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    13542.41                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27186.38                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           6.81                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        6.81                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       6000                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.35                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      9402120.02                       # Average gap between requests
system.physmem.pageHitRate                      82.35                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent               1.05                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                      6806039                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq                4462                       # Transaction distribution
system.membus.trans_dist::ReadResp               4461                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               2                       # Transaction distribution
system.membus.trans_dist::ReadExReq              2824                       # Transaction distribution
system.membus.trans_dist::ReadExResp             2824                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14575                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  14575                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       466240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total              466240                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus                 466240                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy             8931500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           67747998                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                35407535                       # Number of BP lookups
system.cpu.branchPred.condPredicted          21210003                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           1658535                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             19582924                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                16814113                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             85.861095                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 6780652                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               8453                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  191                       # Number of system calls
system.cpu.numCycles                        137007735                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           38995510                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      317974758                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    35407535                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           23594765                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      70934448                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 6878177                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               21511393                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  109                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          1738                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           61                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  37596145                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                512137                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          136651264                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.983546                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.454335                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 66349844     48.55%     48.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  6791529      4.97%     53.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  5702360      4.17%     57.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  6103499      4.47%     62.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  4918940      3.60%     65.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  4085838      2.99%     68.75% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  3180821      2.33%     71.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  4138782      3.03%     74.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 35379651     25.89%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            136651264                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.258435                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.320853                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 45513422                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              16662187                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  66798256                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               2538078                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                5139321                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              7340905                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 69056                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              401756741                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                208904                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                5139321                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 51060721                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 1905439                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         332675                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  63727748                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              14485360                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              394162913                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    18                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1657895                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              10187119                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents            22377                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           432668253                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            2737675688                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1575239963                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         200387111                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             384566193                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 48102060                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              11946                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          11945                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  36528458                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            103595819                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            91394334                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           4295156                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5297473                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  384542604                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               22919                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 374214780                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           1210476                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        34753044                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    100302329                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            799                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     136651264                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.738466                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.024544                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            25105050     18.37%     18.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            19938594     14.59%     32.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            20566375     15.05%     48.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            18171632     13.30%     61.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            24028761     17.58%     78.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            15737538     11.52%     90.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             8814188      6.45%     96.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             3372330      2.47%     99.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              916796      0.67%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       136651264                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                    8713      0.05%      0.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                   4693      0.03%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd             46317      0.26%      0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp              3518      0.02%      0.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt               440      0.00%      0.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 2      0.00%      0.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc           186929      1.05%      1.41% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult             4248      0.02%      1.44% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc        241299      1.36%      2.80% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.80% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                9275439     52.33%     55.13% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               7953254     44.87%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             126461637     33.79%     33.79% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2175765      0.58%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    4      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     34.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         6779975      1.81%     36.19% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     36.19% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         8474577      2.26%     38.45% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         3430301      0.92%     39.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv         1595259      0.43%     39.79% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       20865413      5.58%     45.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult        7172902      1.92%     47.29% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc      7130224      1.91%     49.19% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     49.24% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            101650995     27.16%     76.40% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            88302442     23.60%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              374214780                       # Type of FU issued
system.cpu.iq.rate                           2.731341                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    17724852                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.047365                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          654627146                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         288999508                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    250114053                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           249389006                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes          130333197                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses    118063719                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              263337797                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses               128601835                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         11086522                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      8947071                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       108758                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        14277                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      9018751                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       174712                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          1900                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                5139321                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  272764                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 35129                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           384567184                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            874047                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             103595819                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             91394334                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              11885                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    347                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   280                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          14277                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        1299093                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       369514                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              1668607                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             370257441                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             100364532                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           3957339                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          1661                       # number of nop insts executed
system.cpu.iew.exec_refs                    187583075                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 32009347                       # Number of branches executed
system.cpu.iew.exec_stores                   87218543                       # Number of stores executed
system.cpu.iew.exec_rate                     2.702456                       # Inst execution rate
system.cpu.iew.wb_sent                      368846220                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     368177772                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 183055174                       # num instructions producing a value
system.cpu.iew.wb_consumers                 363803620                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.687277                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.503170                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        35502239                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           1589851                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    131511943                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.654246                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.658719                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     34696225     26.38%     26.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     28452590     21.63%     48.02% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     13345612     10.15%     58.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     11442919      8.70%     66.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     13780020     10.48%     77.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      7417113      5.64%     82.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      3869989      2.94%     85.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      3892889      2.96%     88.89% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     14614586     11.11%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    131511943                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            273037337                       # Number of instructions committed
system.cpu.commit.committedOps              349065061                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      177024331                       # Number of memory references committed
system.cpu.commit.loads                      94648748                       # Number of loads committed
system.cpu.commit.membars                       11033                       # Number of memory barriers committed
system.cpu.commit.branches                   30563497                       # Number of branches committed
system.cpu.commit.fp_insts                  114216705                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 279584611                       # Number of committed integer instructions.
system.cpu.commit.function_calls              6225112                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              14614586                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    501462134                       # The number of ROB reads
system.cpu.rob.rob_writes                   774278104                       # The number of ROB writes
system.cpu.timesIdled                            6640                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          356471                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   273036725                       # Number of Instructions Simulated
system.cpu.committedOps                     349064449                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total             273036725                       # Number of Instructions Simulated
system.cpu.cpi                               0.501792                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.501792                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.992856                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.992856                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1769894079                       # number of integer regfile reads
system.cpu.int_regfile_writes               233026497                       # number of integer regfile writes
system.cpu.fp_regfile_reads                 188140638                       # number of floating regfile reads
system.cpu.fp_regfile_writes                132514898                       # number of floating regfile writes
system.cpu.misc_regfile_reads              1201076625                       # number of misc regfile reads
system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
system.cpu.toL2Bus.throughput                20069641                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          17607                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         17606                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback         1035                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         2841                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         2841                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        31671                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10259                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total             41930                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1013312                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       361280                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total        1374592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus           1374592                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus          256                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy       11777500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      24288488                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy       7388212                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements             13947                       # number of replacements
system.cpu.icache.tags.tagsinuse          1848.346697                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            37578823                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             15836                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           2372.999684                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1848.346697                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.902513                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.902513                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1889                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          205                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            9                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1530                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.922363                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          75208123                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         75208123                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     37578823                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        37578823                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      37578823                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         37578823                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     37578823                       # number of overall hits
system.cpu.icache.overall_hits::total        37578823                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        17320                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         17320                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        17320                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          17320                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        17320                       # number of overall misses
system.cpu.icache.overall_misses::total         17320                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    450229234                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    450229234                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    450229234                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    450229234                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    450229234                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    450229234                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     37596143                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     37596143                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     37596143                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     37596143                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     37596143                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     37596143                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000461                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000461                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000461                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000461                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000461                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000461                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25994.759469                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 25994.759469                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25994.759469                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 25994.759469                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25994.759469                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 25994.759469                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         2351                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                25                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    94.040000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1482                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1482                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1482                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1482                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1482                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1482                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15838                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        15838                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        15838                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        15838                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        15838                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        15838                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    359653509                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    359653509                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    359653509                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    359653509                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    359653509                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    359653509                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000421                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000421                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000421                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000421                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22708.265501                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22708.265501                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22708.265501                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 22708.265501                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22708.265501                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 22708.265501                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         3937.367139                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              13183                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             5383                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.449006                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   378.211483                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2780.743240                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data   778.412416                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.011542                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.084862                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.023755                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.120159                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024         5383                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1           69                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1236                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4007                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.164276                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses           180072                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses          180072                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        12790                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data          299                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          13089                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks         1035                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total         1035                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data           17                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total           17                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        12790                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data          316                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           13106                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        12790                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data          316                       # number of overall hits
system.cpu.l2cache.overall_hits::total          13106                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3044                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data         1470                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         4514                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2824                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2824                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3044                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         4294                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total          7338                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3044                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         4294                       # number of overall misses
system.cpu.l2cache.overall_misses::total         7338                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    215877500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data    110553500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    326431000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    198942750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    198942750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    215877500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    309496250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    525373750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    215877500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    309496250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    525373750                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        15834                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data         1769                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        17603                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks         1035                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total         1035                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data            2                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total            2                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         2841                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         2841                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        15834                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data         4610                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total        20444                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        15834                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data         4610                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total        20444                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.192245                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.830978                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.256434                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994016                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.994016                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.192245                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.931453                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.358932                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.192245                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.931453                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.358932                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70919.021025                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75206.462585                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72315.241471                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70447.149433                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70447.149433                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70919.021025                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72076.443875                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 71596.313709                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70919.021025                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72076.443875                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 71596.313709                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           40                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           52                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           40                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           52                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           40                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           52                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3032                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1430                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         4462                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2824                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         2824                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3032                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         4254                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total         7286                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3032                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         4254                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total         7286                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    177153750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     90029000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    267182750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        20002                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        20002                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    164034250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    164034250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    177153750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    254063250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    431217000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    177153750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    254063250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    431217000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.191487                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.808366                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.253480                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994016                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994016                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.191487                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922777                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.356388                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.191487                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922777                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.356388                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58428.017810                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62957.342657                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59879.594352                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58085.782578                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58085.782578                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58428.017810                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59723.377997                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59184.326105                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58428.017810                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59723.377997                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59184.326105                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements              1413                       # number of replacements
system.cpu.dcache.tags.tagsinuse          3103.986618                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           170973728                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs              4610                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs          37087.576573                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  3103.986618                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.757809                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.757809                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         3197                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          682                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           11                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         2449                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024     0.780518                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         342002086                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        342002086                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     88920204                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        88920204                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     82031597                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       82031597                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        11020                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        11020                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     170951801                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        170951801                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    170951801                       # number of overall hits
system.cpu.dcache.overall_hits::total       170951801                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data         3952                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total          3952                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        21068                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        21068                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data        25020                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total          25020                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data        25020                       # number of overall misses
system.cpu.dcache.overall_misses::total         25020                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data    237491705                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    237491705                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   1258064893                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   1258064893                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       170250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       170250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   1495556598                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   1495556598                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   1495556598                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   1495556598                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     88924156                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     88924156                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     82052665                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     82052665                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11022                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        11022                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    170976821                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    170976821                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    170976821                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    170976821                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000044                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000044                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000257                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.000257                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000181                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000181                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.000146                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.000146                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.000146                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.000146                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60094.054909                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 60094.054909                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59714.490839                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 59714.490839                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85125                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85125                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59774.444365                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59774.444365                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59774.444365                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59774.444365                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        27944                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1224                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               406                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              12                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    68.827586                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          102                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks         1035                       # number of writebacks
system.cpu.dcache.writebacks::total              1035                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data         2181                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         2181                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        18227                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        18227                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        20408                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        20408                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        20408                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        20408                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1771                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total         1771                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2841                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         2841                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data         4612                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total         4612                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data         4612                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total         4612                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    115481540                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    115481540                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    201937248                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total    201937248                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    317418788                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    317418788                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    317418788                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    317418788                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000020                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000020                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000035                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65206.967815                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65206.967815                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71079.636748                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71079.636748                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68824.542064                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68824.542064                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68824.542064                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68824.542064                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------