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---------- Begin Simulation Statistics ----------
sim_seconds 0.525854 # Number of seconds simulated
sim_ticks 525854475000 # Number of ticks simulated
final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1206167 # Simulator instruction rate (inst/s)
host_tick_rate 1819018700 # Simulator tick rate (ticks/s)
host_mem_usage 227092 # Number of bytes of host memory used
host_seconds 289.09 # Real time elapsed on the host
sim_insts 348687131 # Number of instructions simulated
system.physmem.bytes_read 437312 # Number of bytes read from this memory
system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.physmem.num_reads 6833 # Number of read requests responded to by this memory
system.physmem.num_writes 0 # Number of write requests responded to by this memory
system.physmem.num_other 0 # Number of other requests responded to by this memory
system.physmem.bw_read 831622 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read 317654 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total 831622 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
system.cpu.numCycles 1051708950 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 348687131 # Number of instructions executed
system.cpu.num_int_alu_accesses 279584925 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12433363 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 16271153 # number of instructions that are conditional controls
system.cpu.num_int_insts 279584925 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
system.cpu.num_int_register_reads 2212913209 # number of times the integer registers were read
system.cpu.num_int_register_writes 251197915 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
system.cpu.num_mem_refs 177024357 # number of memory refs
system.cpu.num_load_insts 94648758 # Number of load instructions
system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1051708950 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 13796 # number of replacements
system.cpu.icache.tagsinuse 1765.984158 # Cycle average of tags in use
system.cpu.icache.total_refs 348644756 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1765.984158 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.862297 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 348644756 # number of ReadReq hits
system.cpu.icache.demand_hits 348644756 # number of demand (read+write) hits
system.cpu.icache.overall_hits 348644756 # number of overall hits
system.cpu.icache.ReadReq_misses 15603 # number of ReadReq misses
system.cpu.icache.demand_misses 15603 # number of demand (read+write) misses
system.cpu.icache.overall_misses 15603 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 328062000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 328062000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 328062000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 348660359 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 348660359 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 348660359 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000045 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000045 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 21025.572005 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 21025.572005 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 15603 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 15603 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 15603 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 281253000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 281253000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 281253000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1332 # number of replacements
system.cpu.dcache.tagsinuse 3078.396238 # Cycle average of tags in use
system.cpu.dcache.total_refs 176641600 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 39446.538633 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 3078.396238 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.751562 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 94570005 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 82049805 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits 176619810 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 176619810 # number of overall hits
system.cpu.dcache.ReadReq_misses 1606 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 2872 # number of WriteReq misses
system.cpu.dcache.demand_misses 4478 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 4478 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 79898000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 160160000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 240058000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 240058000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 94571611 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 176624288 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 176624288 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 53608.307280 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 53608.307280 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 998 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1606 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 2872 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 4478 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 4478 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 75080000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 151544000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 226624000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 226624000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 48 # number of replacements
system.cpu.l2cache.tagsinuse 3475.672922 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13308 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4883 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.725374 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 3134.059650 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 341.613272 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.095644 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.010425 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 13232 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 998 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 16 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 13248 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 13248 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3977 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 2856 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 6833 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 6833 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 206804000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 148512000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 355316000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 355316000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 17209 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 998 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 20081 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 20081 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.231100 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.994429 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.340272 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.340272 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 2856 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 6833 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 6833 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 114240000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 273320000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231100 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994429 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.340272 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.340272 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
|
