path: root/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.508216                       # Number of seconds simulated
sim_ticks                                508215534000                       # Number of ticks simulated
final_tick                               508215534000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 266071                       # Simulator instruction rate (inst/s)
host_op_rate                                   266071                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              145588775                       # Simulator tick rate (ticks/s)
host_mem_usage                                 258712                       # Number of bytes of host memory used
host_seconds                                  3490.76                       # Real time elapsed on the host
sim_insts                                   928789150                       # Number of instructions simulated
sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            185920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          18520192                       # Number of bytes read from this memory
system.physmem.bytes_read::total             18706112                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       185920                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          185920                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2905                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             289378                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                292283                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               365829                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             36441609                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                36807438                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          365829                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             365829                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           8397445                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                8397445                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           8397445                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              365829                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            36441609                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               45204883                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        292283                       # Number of read requests accepted
system.physmem.writeReqs                        66683                       # Number of write requests accepted
system.physmem.readBursts                      292283                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 18687040                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     19072                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4265984                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  18706112                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      298                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               18032                       # Per bank write bursts
system.physmem.perBankRdBursts::1               18362                       # Per bank write bursts
system.physmem.perBankRdBursts::2               18398                       # Per bank write bursts
system.physmem.perBankRdBursts::3               18335                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18250                       # Per bank write bursts
system.physmem.perBankRdBursts::5               18255                       # Per bank write bursts
system.physmem.perBankRdBursts::6               18321                       # Per bank write bursts
system.physmem.perBankRdBursts::7               18295                       # Per bank write bursts
system.physmem.perBankRdBursts::8               18232                       # Per bank write bursts
system.physmem.perBankRdBursts::9               18236                       # Per bank write bursts
system.physmem.perBankRdBursts::10              18232                       # Per bank write bursts
system.physmem.perBankRdBursts::11              18379                       # Per bank write bursts
system.physmem.perBankRdBursts::12              18271                       # Per bank write bursts
system.physmem.perBankRdBursts::13              18134                       # Per bank write bursts
system.physmem.perBankRdBursts::14              18060                       # Per bank write bursts
system.physmem.perBankRdBursts::15              18193                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4160                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4142                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4099                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4180                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    508215452500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  292283                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    291508                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       465                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        12                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      937                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4046                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4050                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4049                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       103603                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      221.521925                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     143.541969                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     268.372247                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          37864     36.55%     36.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        43808     42.28%     78.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         9097      8.78%     87.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          745      0.72%     88.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1395      1.35%     89.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1153      1.11%     90.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          627      0.61%     91.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          610      0.59%     91.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8304      8.02%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         103603                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4049                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        69.361324                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       34.573478                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      739.455375                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           4041     99.80%     99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215            1      0.02%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359            4      0.10%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-16383            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4049                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4049                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.462336                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.441628                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.843264                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3113     76.88%     76.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                936     23.12%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4049                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2518388500                       # Total ticks spent queuing
system.physmem.totMemAccLat                7993107250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1459925000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        8625.06                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  27375.06                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          36.77                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           8.39                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       36.81                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        8.40                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.35                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.29                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                     203026                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     52001                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   69.53                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.98                       # Row buffer hit rate for writes
system.physmem.avgGap                      1415776.01                       # Average gap between requests
system.physmem.pageHitRate                      71.10                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  390708360                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  213184125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1140250800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            33193711200                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           103572972045                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           214071794250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             352799059260                       # Total energy per rank (pJ)
system.physmem_0.averagePower              694.201008                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   355459552750                       # Time in different power states
system.physmem_0.memoryStateTime::REF     16970200000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    135779058500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  392424480                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  214120500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1136545800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                215492400                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            33193711200                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           103467236760                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           214164544500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             352784075640                       # Total energy per rank (pJ)
system.physmem_1.averagePower              694.171524                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   355611467750                       # Time in different power states
system.physmem_1.memoryStateTime::REF     16970200000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    135627775750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups               123851653                       # Number of BP lookups
system.cpu.branchPred.condPredicted          79872946                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            686743                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            102066131                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                68190141                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             66.809764                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                18697400                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              11224                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups        14052177                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits           14048616                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             3561                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        11655                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    237539296                       # DTB read hits
system.cpu.dtb.read_misses                     195211                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                237734507                       # DTB read accesses
system.cpu.dtb.write_hits                    98305020                       # DTB write hits
system.cpu.dtb.write_misses                      7170                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses                98312190                       # DTB write accesses
system.cpu.dtb.data_hits                    335844316                       # DTB hits
system.cpu.dtb.data_misses                     202381                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                336046697                       # DTB accesses
system.cpu.itb.fetch_hits                   286584409                       # ITB hits
system.cpu.itb.fetch_misses                       119                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               286584528                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   37                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    508215534000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                       1016431068                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   928789150                       # Number of instructions committed
system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                        319592                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.094361                       # CPI: cycles per instruction
system.cpu.ipc                               0.913775                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass            86206875      9.28%      9.28% # Class of committed instruction
system.cpu.op_class_0::IntAlu               486529511     52.38%     61.66% # Class of committed instruction
system.cpu.op_class_0::IntMult                   7040      0.00%     61.67% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     61.67% # Class of committed instruction
system.cpu.op_class_0::FloatAdd              13018262      1.40%     63.07% # Class of committed instruction
system.cpu.op_class_0::FloatCmp               3826477      0.41%     63.48% # Class of committed instruction
system.cpu.op_class_0::FloatCvt               3187663      0.34%     63.82% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    4      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc                0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     63.82% # Class of committed instruction
system.cpu.op_class_0::MemRead              237705247     25.59%     89.42% # Class of committed instruction
system.cpu.op_class_0::MemWrite              98308071     10.58%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                928789150                       # Class of committed instruction
system.cpu.tickCycles                       962815750                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        53615318                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements            776559                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4092.348104                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           320318733                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            780655                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            410.320478                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         905242500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4092.348104                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999108                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999108                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          955                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         1381                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1491                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         643115729                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        643115729                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    222154684                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       222154684                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     98164049                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       98164049                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     320318733                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        320318733                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    320318733                       # number of overall hits
system.cpu.dcache.overall_hits::total       320318733                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       711653                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        711653                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       137151                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       137151                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data       848804                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         848804                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       848804                       # number of overall misses
system.cpu.dcache.overall_misses::total        848804                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  24412597000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  24412597000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10105115500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10105115500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  34517712500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  34517712500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  34517712500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  34517712500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    222866337                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    222866337                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    321167537                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    321167537                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    321167537                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    321167537                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003193                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.003193                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001395                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001395                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002643                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002643                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002643                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002643                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34304.073755                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34304.073755                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73678.759178                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73678.759178                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40666.293396                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40666.293396                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40666.293396                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40666.293396                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks        88481                       # number of writebacks
system.cpu.dcache.writebacks::total             88481                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data            9                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total            9                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68140                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        68140                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        68149                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        68149                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        68149                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        68149                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711644                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       711644                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69011                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        69011                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       780655                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       780655                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       780655                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       780655                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23700262500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  23700262500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5068010000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5068010000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28768272500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  28768272500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28768272500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  28768272500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003193                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003193                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000702                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002431                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002431                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002431                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002431                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33303.537302                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33303.537302                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73437.712828                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73437.712828                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36851.454868                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36851.454868                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36851.454868                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 36851.454868                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements             10580                       # number of replacements
system.cpu.icache.tags.tagsinuse          1690.197843                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           286572082                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             12326                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          23249.398183                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1690.197843                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.825292                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.825292                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1746                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1576                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.852539                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         573181144                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        573181144                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    286572082                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       286572082                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     286572082                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        286572082                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    286572082                       # number of overall hits
system.cpu.icache.overall_hits::total       286572082                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        12327                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         12327                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        12327                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          12327                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        12327                       # number of overall misses
system.cpu.icache.overall_misses::total         12327                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    353123500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    353123500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    353123500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    353123500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    353123500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    353123500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    286584409                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    286584409                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    286584409                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    286584409                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    286584409                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    286584409                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000043                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000043                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000043                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000043                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28646.345421                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28646.345421                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28646.345421                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28646.345421                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28646.345421                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28646.345421                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        10580                       # number of writebacks
system.cpu.icache.writebacks::total             10580                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12327                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        12327                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        12327                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        12327                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        12327                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        12327                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    340797500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    340797500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    340797500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    340797500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    340797500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    340797500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000043                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000043                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27646.426543                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27646.426543                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27646.426543                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 27646.426543                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27646.426543                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 27646.426543                       # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           259960                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32580.630666                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1218282                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           292696                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.162278                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  2624.989355                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    79.480782                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29876.160528                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.080108                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002426                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.911748                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.994282                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32736                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          153                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          302                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2944                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29055                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         13002675                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        13002675                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks        88481                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total        88481                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        10580                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        10580                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         2366                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         2366                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         9421                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         9421                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       488911                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       488911                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         9421                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       491277                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          500698                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         9421                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       491277                       # number of overall hits
system.cpu.l2cache.overall_hits::total         500698                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data        66645                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66645                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2906                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2906                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222733                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       222733                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2906                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       289378                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        292284                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2906                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       289378                       # number of overall misses
system.cpu.l2cache.overall_misses::total       292284                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4939623000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   4939623000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    223388000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    223388000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17499220000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  17499220000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    223388000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  22438843000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  22662231000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    223388000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  22438843000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  22662231000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks        88481                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total        88481                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        10580                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        10580                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        69011                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        69011                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        12327                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        12327                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       711644                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       711644                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        12327                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       780655                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       792982                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        12327                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       780655                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       792982                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.965716                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.965716                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.235743                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.235743                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312984                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312984                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.235743                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.370686                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.368588                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.235743                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.370686                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.368588                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74118.433491                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74118.433491                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76871.300757                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76871.300757                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78565.906264                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78565.906264                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76871.300757                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77541.634126                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77534.969413                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76871.300757                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77541.634126                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77534.969413                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66645                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66645                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2906                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2906                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222733                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222733                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2906                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       289378                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       292284                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2906                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       289378                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       292284                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4273173000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4273173000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    194338000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    194338000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15271890000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15271890000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    194338000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19545063000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  19739401000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    194338000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19545063000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  19739401000                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965716                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965716                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.235743                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.235743                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312984                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312984                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.235743                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370686                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.368588                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.235743                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370686                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.368588                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64118.433491                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64118.433491                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66874.741913                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66874.741913                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68565.906264                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68565.906264                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66874.741913                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67541.634126                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67535.003627                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66874.741913                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67541.634126                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67535.003627                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      1580121                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       787139                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2087                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2087                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp        723970                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       155164                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        10580                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       881355                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        69011                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        69011                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        12327                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       711644                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35233                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337869                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2373102                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1465984                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55624704                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           57090688                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      259960                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               4267712                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      1052942                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.001982                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.044476                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            1050855     99.80%     99.80% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               2087      0.20%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1052942                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      889121500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      18489000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1170982999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
system.membus.pwrStateResidencyTicks::UNDEFINED 508215534000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp             225638                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        66683                       # Transaction distribution
system.membus.trans_dist::CleanEvict           191190                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66645                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66645                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        225638                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842439                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 842439                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22973824                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22973824                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            550156                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  550156    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              550156                       # Request fanout histogram
system.membus.reqLayer0.occupancy           925402000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1556718500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------