path: root/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.639589                       # Number of seconds simulated
sim_ticks                                639588907000                       # Number of ticks simulated
final_tick                               639588907000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 210347                       # Simulator instruction rate (inst/s)
host_op_rate                                   210347                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               73797228                       # Simulator tick rate (ticks/s)
host_mem_usage                                 229080                       # Number of bytes of host memory used
host_seconds                                  8666.84                       # Real time elapsed on the host
sim_insts                                  1823043370                       # Number of instructions simulated
sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            191360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          94464192                       # Number of bytes read from this memory
system.physmem.bytes_read::total             94655552                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       191360                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          191360                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4281472                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4281472                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2990                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1476003                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1478993                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66898                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66898                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               299192                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            147695169                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               147994362                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          299192                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             299192                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           6694100                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6694100                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           6694100                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              299192                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           147695169                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              154688461                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    525683715                       # DTB read hits
system.cpu.dtb.read_misses                     628896                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                526312611                       # DTB read accesses
system.cpu.dtb.write_hits                   287304184                       # DTB write hits
system.cpu.dtb.write_misses                     53890                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               287358074                       # DTB write accesses
system.cpu.dtb.data_hits                    812987899                       # DTB hits
system.cpu.dtb.data_misses                     682786                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                813670685                       # DTB accesses
system.cpu.itb.fetch_hits                   398461552                       # ITB hits
system.cpu.itb.fetch_misses                      1212                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               398462764                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   39                       # Number of system calls
system.cpu.numCycles                       1279177815                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                391601012                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          255930815                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect           27097905                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups             318432805                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                256621752                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                 59044090                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect                7305                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          417206849                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     3304631660                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   391601012                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          315665842                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     634205086                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               158948618                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               96266839                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  158                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         11708                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                 398461552                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               8907646                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1279053519                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.583654                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.145594                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                644848433     50.42%     50.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 60073670      4.70%     55.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 44904383      3.51%     58.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 71013010      5.55%     64.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                124436565      9.73%     73.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 45667903      3.57%     77.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 41114141      3.21%     80.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  7023739      0.55%     81.24% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                239971675     18.76%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1279053519                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.306135                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.583403                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                450209575                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              79019815                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 608453320                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              10020119                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              131350690                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             33655569                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 12307                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3205531959                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 46810                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              131350690                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                478839352                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                32033074                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          25872                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 588505763                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              48298768                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             3118953725                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   371                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                   8014                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              42155636                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2071308237                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3619384197                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3501684594                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         117699603                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                686339167                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               4232                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            137                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 140575935                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            734762265                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           354500186                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          67932920                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          9138793                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2625466002                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                 122                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2176735177                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          17945547                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       802302909                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    703322223                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             83                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1279053519                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.701833                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.797036                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           464081398     36.28%     36.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           216592353     16.93%     53.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           250622762     19.59%     72.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           121884176      9.53%     82.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           104836053      8.20%     90.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            77987896      6.10%     96.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            21570720      1.69%     98.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            17288528      1.35%     99.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             4189633      0.33%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1279053519                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1140853      3.19%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.19% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               24076891     67.30%     70.49% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              10558644     29.51%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1247700404     57.32%     57.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                16695      0.00%     57.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd            28729941      1.32%     58.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp             8254693      0.38%     59.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt             7204651      0.33%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.35% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            586556392     26.95%     86.30% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           298269645     13.70%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2176735177                       # Type of FU issued
system.cpu.iq.rate                           1.701667                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    35776388                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.016436                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5534048167                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3341408955                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2010160977                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           152197641                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           86432816                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     74384435                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2134737053                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                77771760                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         67976479                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    223692239                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        13198                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        75649                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    143705290                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         4417                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            29                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              131350690                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 3811054                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                200562                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2981894857                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           2707472                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             734762265                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            354500186                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                122                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 131033                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  4888                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          75649                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       27118847                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect        31958                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             27150805                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2088347607                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             526312810                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          88387570                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                     356428733                       # number of nop insts executed
system.cpu.iew.exec_refs                    813671363                       # number of memory reference insts executed
system.cpu.iew.exec_branches                280895404                       # Number of branches executed
system.cpu.iew.exec_stores                  287358553                       # Number of stores executed
system.cpu.iew.exec_rate                     1.632570                       # Inst execution rate
system.cpu.iew.wb_sent                     2087345359                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2084545412                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1181911333                       # num instructions producing a value
system.cpu.iew.wb_consumers                1746825923                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.629598                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.676605                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts     2008987604                       # The number of committed instructions
system.cpu.commit.commitCommittedOps       2008987604                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts       956239558                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          27085717                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1147702829                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.750442                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.504523                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    533397723     46.48%     46.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    226612269     19.74%     66.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    118218768     10.30%     76.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     56744377      4.94%     81.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     50032490      4.36%     85.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     24020067      2.09%     87.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     19167450      1.67%     89.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     15607807      1.36%     90.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8    103901878      9.05%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1147702829                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           2008987604                       # Number of instructions committed
system.cpu.commit.committedOps             2008987604                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      721864922                       # Number of memory references committed
system.cpu.commit.loads                     511070026                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  266706457                       # Number of branches committed
system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
system.cpu.commit.bw_lim_events             103901878                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   4003391703                       # The number of ROB reads
system.cpu.rob.rob_writes                  6061807983                       # The number of ROB writes
system.cpu.timesIdled                            3462                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          124296                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
system.cpu.committedOps                    1823043370                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
system.cpu.cpi                               0.701672                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.701672                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.425168                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.425168                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2657999656                       # number of integer regfile reads
system.cpu.int_regfile_writes              1510398630                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  80463471                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 53540440                       # number of floating regfile writes
system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.icache.replacements                   8417                       # number of replacements
system.cpu.icache.tagsinuse               1667.677082                       # Cycle average of tags in use
system.cpu.icache.total_refs                398450176                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  10137                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               39306.518299                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1667.677082                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.814295                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.814295                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    398450176                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       398450176                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     398450176                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        398450176                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    398450176                       # number of overall hits
system.cpu.icache.overall_hits::total       398450176                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        11376                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         11376                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        11376                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          11376                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        11376                       # number of overall misses
system.cpu.icache.overall_misses::total         11376                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    188382000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    188382000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    188382000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    188382000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    188382000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    188382000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    398461552                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    398461552                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    398461552                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    398461552                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    398461552                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    398461552                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16559.599156                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16559.599156                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16559.599156                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16559.599156                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16559.599156                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16559.599156                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1238                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1238                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1238                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1238                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1238                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1238                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10138                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        10138                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        10138                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        10138                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        10138                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        10138                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    122862500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    122862500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    122862500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    122862500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    122862500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    122862500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12119.007694                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12119.007694                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12119.007694                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12119.007694                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12119.007694                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12119.007694                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1527982                       # number of replacements
system.cpu.dcache.tagsinuse               4095.064488                       # Cycle average of tags in use
system.cpu.dcache.total_refs                666017344                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1532078                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 434.715037                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              264095000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4095.064488                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999772                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999772                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    455774339                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       455774339                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    210242956                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      210242956                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           49                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           49                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data     666017295                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        666017295                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    666017295                       # number of overall hits
system.cpu.dcache.overall_hits::total       666017295                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1928410                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1928410                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       551940                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       551940                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2480350                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2480350                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2480350                       # number of overall misses
system.cpu.dcache.overall_misses::total       2480350                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  71225328000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  71225328000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  20805642991                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  20805642991                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        20500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        20500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  92030970991                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  92030970991                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  92030970991                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  92030970991                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    457702749                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    457702749                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           50                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           50                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    668497645                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    668497645                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    668497645                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    668497645                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004213                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004213                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002618                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.002618                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.020000                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.020000                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.003710                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.003710                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.003710                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.003710                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36934.743130                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 36934.743130                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37695.479565                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37695.479565                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        20500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        20500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37104.026041                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37104.026041                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37104.026041                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 37104.026041                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        98500                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        22000                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                16                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs  6156.250000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets        22000                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       109405                       # number of writebacks
system.cpu.dcache.writebacks::total            109405                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       467937                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       467937                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       480335                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       480335                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       948272                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       948272                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       948272                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       948272                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460473                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1460473                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71605                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        71605                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1532078                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1532078                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1532078                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1532078                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  49721165500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  49721165500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2483602000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2483602000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  52204767500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  52204767500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  52204767500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  52204767500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003191                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003191                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000340                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000340                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002292                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002292                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002292                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002292                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34044.563302                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34044.563302                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34684.756651                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34684.756651                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34074.484132                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34074.484132                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34074.484132                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34074.484132                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements               1480674                       # number of replacements
system.cpu.l2cache.tagsinuse             32705.756030                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   66279                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs               1513408                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.043795                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks  3232.284223                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     45.882783                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  29427.589024                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.098641                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.001400                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.898059                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.998100                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         7148                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        51323                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          58471                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       109405                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       109405                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4752                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4752                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         7148                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        56075                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           63223                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         7148                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        56075                       # number of overall hits
system.cpu.l2cache.overall_hits::total          63223                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2990                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1409150                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1412140                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66853                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66853                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2990                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1476003                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1478993                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2990                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1476003                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1478993                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    102622500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48197202500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  48299825000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2339465500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   2339465500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    102622500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  50536668000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  50639290500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    102622500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  50536668000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  50639290500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        10138                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1460473                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1470611                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       109405                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       109405                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        71605                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        71605                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        10138                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1532078                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1542216                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        10138                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1532078                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1542216                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.294930                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.964859                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.960240                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.933636                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.933636                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.294930                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.963399                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.959005                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.294930                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.963399                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.959005                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34321.906355                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34203.031970                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34203.283669                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34994.173784                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34994.173784                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34321.906355                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34238.865368                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34239.033248                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34321.906355                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34238.865368                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34239.033248                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs        40000                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs               11                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs  3636.363636                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66898                       # number of writebacks
system.cpu.l2cache.writebacks::total            66898                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2990                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1409150                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1412140                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66853                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66853                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2990                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1476003                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1478993                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2990                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1476003                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1478993                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     92982500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  43684578500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  43777561000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2138150500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2138150500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     92982500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  45822729000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  45915711500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     92982500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  45822729000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  45915711500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.294930                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.964859                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.960240                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.933636                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.933636                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.294930                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963399                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.959005                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.294930                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963399                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.959005                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.826087                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.658908                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31000.864645                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31982.865391                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31982.865391                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.826087                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31045.146250                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31045.252750                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.826087                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31045.146250                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31045.252750                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------