path: root/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.276406                       # Number of seconds simulated
sim_ticks                                276406029500                       # Number of ticks simulated
final_tick                               276406029500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 130885                       # Simulator instruction rate (inst/s)
host_op_rate                                   130885                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               42946592                       # Simulator tick rate (ticks/s)
host_mem_usage                                 301528                       # Number of bytes of host memory used
host_seconds                                  6436.04                       # Real time elapsed on the host
sim_insts                                   842382029                       # Number of instructions simulated
sim_ops                                     842382029                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            173952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          18519360                       # Number of bytes read from this memory
system.physmem.bytes_read::total             18693312                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       173952                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          173952                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2718                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             289365                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                292083                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               629335                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             67000564                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                67629900                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          629335                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             629335                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          15440011                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               15440011                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          15440011                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              629335                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            67000564                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               83069910                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        292083                       # Number of read requests accepted
system.physmem.writeReqs                        66683                       # Number of write requests accepted
system.physmem.readBursts                      292083                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 18672064                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     21248                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4266752                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  18693312                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      332                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               18010                       # Per bank write bursts
system.physmem.perBankRdBursts::1               18319                       # Per bank write bursts
system.physmem.perBankRdBursts::2               18376                       # Per bank write bursts
system.physmem.perBankRdBursts::3               18330                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18231                       # Per bank write bursts
system.physmem.perBankRdBursts::5               18221                       # Per bank write bursts
system.physmem.perBankRdBursts::6               18322                       # Per bank write bursts
system.physmem.perBankRdBursts::7               18297                       # Per bank write bursts
system.physmem.perBankRdBursts::8               18226                       # Per bank write bursts
system.physmem.perBankRdBursts::9               18218                       # Per bank write bursts
system.physmem.perBankRdBursts::10              18207                       # Per bank write bursts
system.physmem.perBankRdBursts::11              18389                       # Per bank write bursts
system.physmem.perBankRdBursts::12              18249                       # Per bank write bursts
system.physmem.perBankRdBursts::13              18121                       # Per bank write bursts
system.physmem.perBankRdBursts::14              18052                       # Per bank write bursts
system.physmem.perBankRdBursts::15              18183                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4160                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4142                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4099                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4192                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    276405940000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  292083                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    216501                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     47240                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     27808                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       172                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      907                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      908                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2525                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4059                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4068                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4061                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4088                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4063                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4062                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4993                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4350                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4058                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4143                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4057                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4059                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       16                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        99437                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      230.668262                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     148.414135                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     279.665008                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          34391     34.59%     34.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        42842     43.08%     77.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        10220     10.28%     87.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          417      0.42%     88.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          400      0.40%     88.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          621      0.62%     89.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          466      0.47%     89.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1450      1.46%     91.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8630      8.68%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          99437                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4053                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        71.663212                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       34.607328                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      761.755251                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           4044     99.78%     99.78% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359            4      0.10%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15360-16383            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4053                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4053                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.449050                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.428679                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.836709                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3145     77.60%     77.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                905     22.33%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                  2      0.05%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4053                       # Writes before turning the bus around for reads
system.physmem.totQLat                     3647206250                       # Total ticks spent queuing
system.physmem.totMemAccLat                9117537500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1458755000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12501.09                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31251.09                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          67.55                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          15.44                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       67.63                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       15.44                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.65                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.53                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.12                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.13                       # Average write queue length when enqueuing
system.physmem.readRowHits                     206989                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     51984                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   70.95                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  77.96                       # Row buffer hit rate for writes
system.physmem.avgGap                       770435.16                       # Average gap between requests
system.physmem.pageHitRate                      72.25                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  373947840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  204039000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1139408400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            18053371440                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            80174383695                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            95514202500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             195675791355                       # Total energy per rank (pJ)
system.physmem_0.averagePower              707.933114                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   158383013500                       # Time in different power states
system.physmem_0.memoryStateTime::REF      9229740000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    108791696000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  377742960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  206109750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1135890600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                215570160                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            18053371440                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            80329865445                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            95377815000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             195696365355                       # Total energy per rank (pJ)
system.physmem_1.averagePower              708.007549                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   158148138750                       # Time in different power states
system.physmem_1.memoryStateTime::REF      9229740000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    109026483750                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               192576076                       # Number of BP lookups
system.cpu.branchPred.condPredicted         126054565                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          11561227                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            137875170                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               126274438                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             91.586062                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                28678363                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect                136                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    242441387                       # DTB read hits
system.cpu.dtb.read_misses                     312131                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                242753518                       # DTB read accesses
system.cpu.dtb.write_hits                   135445935                       # DTB write hits
system.cpu.dtb.write_misses                     31631                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               135477566                       # DTB write accesses
system.cpu.dtb.data_hits                    377887322                       # DTB hits
system.cpu.dtb.data_misses                     343762                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                378231084                       # DTB accesses
system.cpu.itb.fetch_hits                   194828154                       # ITB hits
system.cpu.itb.fetch_misses                       242                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               194828396                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   37                       # Number of system calls
system.cpu.numCycles                        552812060                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          198850471                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1637321626                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   192576076                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          154952801                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     341917067                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                23591046                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          6993                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 194828154                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               7885913                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          552570202                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.963102                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.176487                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                236054473     42.72%     42.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 29638362      5.36%     48.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 21702458      3.93%     52.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 35773228      6.47%     58.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 67707960     12.25%     70.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 21595876      3.91%     74.65% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 19328628      3.50%     78.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  3978060      0.72%     78.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                116791157     21.14%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            552570202                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.348357                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.961805                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                166802287                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              90542864                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 271199395                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              12236841                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               11788815                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             15468328                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                  6932                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1567838176                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 24969                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               11788815                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                173688859                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                60716441                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          13717                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 276533617                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              29828753                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1529250735                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  8190                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2401406                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               20516503                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                7198838                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          1021411513                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1760089033                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1720202399                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          39886633                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             638967158                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                382444355                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               1364                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             84                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                   9081858                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            369185264                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           173801333                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          40211283                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         11128775                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1296786218                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  72                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1011356527                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           8787388                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       454404260                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    422537101                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             35                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     552570202                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.830277                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.913640                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           197270443     35.70%     35.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            90785192     16.43%     52.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            90547416     16.39%     68.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            58763251     10.63%     79.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            57064914     10.33%     89.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            29634790      5.36%     94.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            16885134      3.06%     97.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             7510156      1.36%     99.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             4108906      0.74%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       552570202                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 2519726     10.56%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               15983640     67.00%     77.56% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               5352814     22.44%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              1276      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             577739239     57.13%     57.13% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                 7929      0.00%     57.13% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.13% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd            13232477      1.31%     58.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp             3826542      0.38%     58.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt             3339799      0.33%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            274563645     27.15%     86.29% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           138645616     13.71%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1011356527                       # Type of FU issued
system.cpu.iq.rate                           1.829476                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    23856180                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023588                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2536915249                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1709850818                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    936642710                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads            71011575                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           41384719                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     34526976                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              998747828                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                36463603                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         49725855                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    131674667                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses      1209013                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        45363                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     75500133                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         2715                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          4018                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               11788815                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                59738270                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                197040                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1470367053                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts             17961                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             369185264                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            173801333                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 72                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  15881                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                192528                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          45363                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       11555967                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect        14465                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             11570432                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             973002630                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             242753693                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          38353897                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                     173580763                       # number of nop insts executed
system.cpu.iew.exec_refs                    378231547                       # number of memory reference insts executed
system.cpu.iew.exec_branches                128483828                       # Number of branches executed
system.cpu.iew.exec_stores                  135477854                       # Number of stores executed
system.cpu.iew.exec_rate                     1.760097                       # Inst execution rate
system.cpu.iew.wb_sent                      971735885                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     971169686                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 554962956                       # num instructions producing a value
system.cpu.iew.wb_consumers                 830927766                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.756781                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.667884                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       534548617                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          11554520                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    481206030                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.929709                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.612045                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    204042568     42.40%     42.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    101511322     21.10%     63.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     52351761     10.88%     74.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     25424969      5.28%     79.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     20905527      4.34%     84.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      8991227      1.87%     85.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     10032438      2.08%     87.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      6244738      1.30%     89.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     51701480     10.74%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    481206030                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            928587628                       # Number of instructions committed
system.cpu.commit.committedOps              928587628                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      335811797                       # Number of memory references committed
system.cpu.commit.loads                     237510597                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  123111018                       # Number of branches committed
system.cpu.commit.fp_insts                   33436273                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 821934723                       # Number of committed integer instructions.
system.cpu.commit.function_calls             18524163                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass     86206875      9.28%      9.28% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        486529510     52.39%     61.68% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult            7040      0.00%     61.68% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.68% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd       13018262      1.40%     63.08% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp        3826477      0.41%     63.49% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt        3187663      0.34%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             4      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     63.84% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       237510597     25.58%     89.41% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       98301200     10.59%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         928587628                       # Class of committed instruction
system.cpu.commit.bw_lim_events              51701480                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1890019657                       # The number of ROB reads
system.cpu.rob.rob_writes                  2997637733                       # The number of ROB writes
system.cpu.timesIdled                            3185                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          241858                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   842382029                       # Number of Instructions Simulated
system.cpu.committedOps                     842382029                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.656249                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.656249                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.523813                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.523813                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1234257247                       # number of integer regfile reads
system.cpu.int_regfile_writes               703449538                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  36844878                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 24462480                       # number of floating regfile writes
system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.dcache.tags.replacements            777154                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4092.899235                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           288564425                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            781250                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            369.362464                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         369553500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4092.899235                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999243                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999243                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          297                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          968                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         2490                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4          256                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         582801760                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        582801760                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    191156368                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       191156368                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     97408043                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       97408043                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           14                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           14                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data     288564411                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        288564411                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    288564411                       # number of overall hits
system.cpu.dcache.overall_hits::total       288564411                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1552672                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1552672                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       893157                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       893157                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2445829                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2445829                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2445829                       # number of overall misses
system.cpu.dcache.overall_misses::total       2445829                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  83271101000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  83271101000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  62352545333                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  62352545333                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        82500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        82500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 145623646333                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 145623646333                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 145623646333                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 145623646333                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    192709040                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    192709040                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           15                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           15                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    291010240                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    291010240                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    291010240                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    291010240                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008057                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.008057                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009086                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.009086                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.066667                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.066667                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.008405                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.008405                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.008405                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.008405                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53630.838323                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 53630.838323                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69811.405311                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69811.405311                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        82500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        82500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59539.586101                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 59539.586101                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59539.586101                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 59539.586101                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        22515                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        72899                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               341                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             517                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.026393                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   141.003868                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        88880                       # number of writebacks
system.cpu.dcache.writebacks::total             88880                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       840227                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       840227                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       824352                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       824352                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1664579                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1664579                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1664579                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1664579                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712445                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       712445                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68805                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        68805                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       781250                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       781250                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       781250                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       781250                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24193547500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  24193547500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5688085497                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5688085497                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29881632997                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  29881632997                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29881632997                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  29881632997                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003697                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003697                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000700                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000700                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002685                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002685                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002685                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002685                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33958.477497                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33958.477497                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82669.653325                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82669.653325                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38248.490236                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 38248.490236                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38248.490236                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 38248.490236                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements              4598                       # number of replacements
system.cpu.icache.tags.tagsinuse          1641.391736                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           194819915                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs              6300                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          30923.796032                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1641.391736                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.801461                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.801461                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1702                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           81                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1537                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.831055                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         389662608                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        389662608                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    194819915                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       194819915                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     194819915                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        194819915                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    194819915                       # number of overall hits
system.cpu.icache.overall_hits::total       194819915                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         8239                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          8239                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         8239                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           8239                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         8239                       # number of overall misses
system.cpu.icache.overall_misses::total          8239                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    351244499                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    351244499                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    351244499                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    351244499                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    351244499                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    351244499                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    194828154                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    194828154                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    194828154                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    194828154                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    194828154                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    194828154                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000042                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000042                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000042                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42631.933366                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42631.933366                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42631.933366                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42631.933366                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42631.933366                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42631.933366                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          510                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    46.363636                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1938                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1938                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1938                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1938                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1938                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1938                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6301                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         6301                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         6301                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         6301                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         6301                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         6301                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    261165999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    261165999                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    261165999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    261165999                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    261165999                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    261165999                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000032                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41448.341374                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41448.341374                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41448.341374                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 41448.341374                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41448.341374                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41448.341374                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           259305                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32630.134515                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1207948                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           292043                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.136199                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  2512.609153                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    65.430826                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 30052.094536                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.076679                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001997                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.917117                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.995793                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32738                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          159                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          211                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          533                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5296                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26539                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999084                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         12915272                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        12915272                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks        88880                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total        88880                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         2178                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         2178                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3582                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total         3582                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       489707                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       489707                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst         3582                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       491885                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          495467                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         3582                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       491885                       # number of overall hits
system.cpu.l2cache.overall_hits::total         495467                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data        66627                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66627                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2719                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2719                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222738                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       222738                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2719                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       289365                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        292084                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2719                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       289365                       # number of overall misses
system.cpu.l2cache.overall_misses::total       292084                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5561753000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5561753000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    214081500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    214081500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17977592000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  17977592000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    214081500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  23539345000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  23753426500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    214081500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  23539345000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  23753426500                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks        88880                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total        88880                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        68805                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        68805                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6301                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total         6301                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       712445                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       712445                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         6301                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       781250                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       787551                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         6301                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       781250                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       787551                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.968345                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.968345                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.431519                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.431519                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312639                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312639                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.431519                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.370387                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.370876                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.431519                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.370387                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.370876                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83475.963198                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83475.963198                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78735.380655                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78735.380655                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80711.831838                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80711.831838                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78735.380655                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81348.279854                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81323.956465                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78735.380655                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81348.279854                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81323.956465                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          394                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          394                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66627                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66627                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2719                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2719                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222738                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222738                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2719                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       289365                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       292084                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2719                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       289365                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       292084                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4895483000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4895483000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    186901500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    186901500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15750212000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15750212000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    186901500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20645695000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  20832596500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    186901500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20645695000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  20832596500                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.968345                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.968345                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.431519                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.431519                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312639                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312639                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.431519                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370387                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.370876                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.431519                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370387                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.370876                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73475.963198                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73475.963198                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68739.058477                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68739.058477                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70711.831838                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70711.831838                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68739.058477                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71348.279854                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71323.990701                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp        718745                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       155563                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       885494                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        68805                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        68805                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq         6301                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       712445                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17199                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2339654                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2356853                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       403200                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55688320                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           56091520                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      259305                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1828608                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.141805                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.348850                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            1569303     85.82%     85.82% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             259305     14.18%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1828608                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      873531500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy       9450000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1171875499                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             225456                       # Transaction distribution
system.membus.trans_dist::Writeback             66683                       # Transaction distribution
system.membus.trans_dist::CleanEvict           191030                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66627                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66627                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        225456                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       841879                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 841879                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22961024                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22961024                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            549796                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  549796    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              549796                       # Request fanout histogram
system.membus.reqLayer0.occupancy           880960000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1551840500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)

---------- End Simulation Statistics   ----------