path: root/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.631518                       # Number of seconds simulated
sim_ticks                                631518097500                       # Number of ticks simulated
final_tick                               631518097500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 141288                       # Simulator instruction rate (inst/s)
host_op_rate                                   141288                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               48943367                       # Simulator tick rate (ticks/s)
host_mem_usage                                 266484                       # Number of bytes of host memory used
host_seconds                                 12903.04                       # Real time elapsed on the host
sim_insts                                  1823043370                       # Number of instructions simulated
sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            176128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          30295488                       # Number of bytes read from this memory
system.physmem.bytes_read::total             30471616                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       176128                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          176128                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4282112                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4282112                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2752                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             473367                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                476119                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66908                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66908                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               278896                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             47972478                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                48251374                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          278896                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             278896                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           6780664                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6780664                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           6780664                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              278896                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            47972478                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               55032038                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        476119                       # Number of read requests accepted
system.physmem.writeReqs                        66908                       # Number of write requests accepted
system.physmem.readBursts                      476119                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66908                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 30465984                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      5632                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4281664                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  30471616                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4282112                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                       88                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               29449                       # Per bank write bursts
system.physmem.perBankRdBursts::1               29798                       # Per bank write bursts
system.physmem.perBankRdBursts::2               29850                       # Per bank write bursts
system.physmem.perBankRdBursts::3               29793                       # Per bank write bursts
system.physmem.perBankRdBursts::4               29695                       # Per bank write bursts
system.physmem.perBankRdBursts::5               29771                       # Per bank write bursts
system.physmem.perBankRdBursts::6               29867                       # Per bank write bursts
system.physmem.perBankRdBursts::7               29856                       # Per bank write bursts
system.physmem.perBankRdBursts::8               29771                       # Per bank write bursts
system.physmem.perBankRdBursts::9               29894                       # Per bank write bursts
system.physmem.perBankRdBursts::10              29844                       # Per bank write bursts
system.physmem.perBankRdBursts::11              29915                       # Per bank write bursts
system.physmem.perBankRdBursts::12              29793                       # Per bank write bursts
system.physmem.perBankRdBursts::13              29587                       # Per bank write bursts
system.physmem.perBankRdBursts::14              29511                       # Per bank write bursts
system.physmem.perBankRdBursts::15              29637                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4160                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4142                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4099                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4334                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4241                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    631518039500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  476119                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66908                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    408579                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     66870                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       429                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      2991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     2992                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     3005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     2994                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     3962                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     3023                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2994                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2995                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2994                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3015                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2993                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     2991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3033                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       182335                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      190.554573                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     126.681752                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     408.631079                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64             68422     37.53%     37.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128            48844     26.79%     64.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192            37964     20.82%     85.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256            20159     11.06%     96.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320              264      0.14%     96.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384              246      0.13%     96.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448              141      0.08%     96.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512              184      0.10%     96.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576              113      0.06%     96.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640              137      0.08%     96.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704               96      0.05%     96.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768              186      0.10%     96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832               81      0.04%     96.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896              159      0.09%     97.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960              151      0.08%     97.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024             133      0.07%     97.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088             108      0.06%     97.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152             148      0.08%     97.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216             143      0.08%     97.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280              80      0.04%     97.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344             131      0.07%     97.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408            1760      0.97%     98.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472            1531      0.84%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536              10      0.01%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600              19      0.01%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664              18      0.01%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728               8      0.00%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792              14      0.01%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856              14      0.01%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920              13      0.01%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984              14      0.01%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048               6      0.00%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112              10      0.01%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176              10      0.01%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240              20      0.01%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304              12      0.01%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368              11      0.01%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432              18      0.01%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496              13      0.01%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560              12      0.01%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624              17      0.01%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688              12      0.01%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752              11      0.01%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816              14      0.01%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880              18      0.01%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944              12      0.01%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008              10      0.01%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072              14      0.01%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136              17      0.01%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200              14      0.01%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264              13      0.01%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328               6      0.00%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392              12      0.01%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456               9      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520               8      0.00%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584              11      0.01%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648              18      0.01%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712               9      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776              16      0.01%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840              12      0.01%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904              17      0.01%     99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968              14      0.01%     99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032              15      0.01%     99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096               5      0.00%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160              16      0.01%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224              14      0.01%     99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288              17      0.01%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352              13      0.01%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416              15      0.01%     99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480              11      0.01%     99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544              18      0.01%     99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608              12      0.01%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672               8      0.00%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736               9      0.00%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800              12      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864               6      0.00%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928              11      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992              11      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056              15      0.01%     99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120              12      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184              12      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248              11      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312              16      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376              12      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440              11      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504              13      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568              16      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632              12      0.01%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696              12      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760              17      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824              10      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888              11      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952              22      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016              11      0.01%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080               8      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144              12      0.01%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208              26      0.01%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272              26      0.01%     99.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336              39      0.02%     99.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400              37      0.02%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464               7      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528               7      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592               6      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656               3      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720               7      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784               8      0.00%     99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848              54      0.03%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128               1      0.00%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         182335                       # Bytes accessed per row activation
system.physmem.totQLat                     2888041500                       # Total ticks spent queuing
system.physmem.totMemAccLat               14116019000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2380155000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  8847822500                       # Total ticks spent accessing banks
system.physmem.avgQLat                        6066.92                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    18586.65                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29653.57                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          48.24                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           6.78                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       48.25                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        6.78                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        10.28                       # Average write queue length when enqueuing
system.physmem.readRowHits                     310714                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     49883                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   65.27                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.55                       # Row buffer hit rate for writes
system.physmem.avgGap                      1162958.82                       # Average gap between requests
system.physmem.pageHitRate                      66.42                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent              25.73                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     55031937                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              409266                       # Transaction distribution
system.membus.trans_dist::ReadResp             409265                       # Transaction distribution
system.membus.trans_dist::Writeback             66908                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66853                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66853                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019145                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1019145                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34753664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            34753664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               34753664                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1230653000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4488013000                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
system.cpu.branchPred.lookups               388926557                       # Number of BP lookups
system.cpu.branchPred.condPredicted         255987580                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          25808786                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            317451636                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               258383726                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             81.393100                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                57269217                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               6785                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    522276153                       # DTB read hits
system.cpu.dtb.read_misses                     591029                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                522867182                       # DTB read accesses
system.cpu.dtb.write_hits                   283024283                       # DTB write hits
system.cpu.dtb.write_misses                     50282                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               283074565                       # DTB write accesses
system.cpu.dtb.data_hits                    805300436                       # DTB hits
system.cpu.dtb.data_misses                     641311                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                805941747                       # DTB accesses
system.cpu.itb.fetch_hits                   394923337                       # ITB hits
system.cpu.itb.fetch_misses                       673                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               394924010                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   39                       # Number of system calls
system.cpu.numCycles                       1263036196                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          410109211                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     3275361916                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   388926557                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          315652943                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     630278695                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               157942219                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               76359250                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  149                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          7183                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           36                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 394923337                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes              11250821                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1248398015                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.623652                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.139094                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                618119320     49.51%     49.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 57470502      4.60%     54.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 43321703      3.47%     57.59% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 71848580      5.76%     63.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                129169735     10.35%     73.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 46220345      3.70%     77.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 41223037      3.30%     80.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  7614963      0.61%     81.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                233409830     18.70%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1248398015                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.307930                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.593245                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                438388188                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              62722157                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 606598506                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               9057712                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              131631452                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             31714965                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 12425                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3194311917                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 46335                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              131631452                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                467678490                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                27888697                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          27235                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 586017174                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              35154967                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             3095577928                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   161                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  15278                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              28853292                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2054701915                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3579840201                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3494452831                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          85387369                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                669732845                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               4230                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts             93                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 109697167                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            743928173                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           351370571                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          69056444                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          8824928                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2623617017                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  88                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2160251370                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          17943532                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       800506396                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    726504541                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             49                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1248398015                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.730419                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.803325                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           451794383     36.19%     36.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           196881070     15.77%     51.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           251357257     20.13%     72.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           120660417      9.67%     81.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           104720930      8.39%     90.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            79314006      6.35%     96.50% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            24236778      1.94%     98.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            17665275      1.42%     99.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             1767899      0.14%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1248398015                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1146213      3.11%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.11% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               25664248     69.68%     72.79% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              10022787     27.21%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1234386708     57.14%     57.14% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                17098      0.00%     57.14% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.14% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd            27851280      1.29%     58.43% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp             8254692      0.38%     58.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt             7204649      0.33%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.15% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            589426190     27.29%     86.43% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           293107997     13.57%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2160251370                       # Type of FU issued
system.cpu.iq.rate                           1.710364                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    36833248                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.017050                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5472576315                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3336085104                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1990052080                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           151101220                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           88112403                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     73609796                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2119632114                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                77449752                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         62130294                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    232858147                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        12904                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        76517                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    140575675                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         4420                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          2986                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              131631452                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                13854870                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                540713                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2987064962                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            734569                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             743928173                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            351370571                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 88                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 134613                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  1496                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          76517                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       25801220                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect        30372                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             25831592                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2066130188                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             522867337                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          94121182                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                     363447857                       # number of nop insts executed
system.cpu.iew.exec_refs                    805942372                       # number of memory reference insts executed
system.cpu.iew.exec_branches                277625839                       # Number of branches executed
system.cpu.iew.exec_stores                  283075035                       # Number of stores executed
system.cpu.iew.exec_rate                     1.635844                       # Inst execution rate
system.cpu.iew.wb_sent                     2066015512                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2063661876                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1180966909                       # num instructions producing a value
system.cpu.iew.wb_consumers                1753315236                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.633890                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.673562                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       961121272                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          25796748                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1116766563                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.798932                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.506928                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    497624739     44.56%     44.56% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    228755329     20.48%     65.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    119853189     10.73%     75.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     58815833      5.27%     81.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     50567042      4.53%     85.57% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     24161277      2.16%     87.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     19140455      1.71%     89.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     16628477      1.49%     90.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8    101220222      9.06%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1116766563                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           2008987604                       # Number of instructions committed
system.cpu.commit.committedOps             2008987604                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      721864922                       # Number of memory references committed
system.cpu.commit.loads                     511070026                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  266706457                       # Number of branches committed
system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
system.cpu.commit.bw_lim_events             101220222                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   3980018807                       # The number of ROB reads
system.cpu.rob.rob_writes                  6071851296                       # The number of ROB writes
system.cpu.timesIdled                          346634                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        14638181                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
system.cpu.committedOps                    1823043370                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
system.cpu.cpi                               0.692817                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.692817                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.443382                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.443382                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2627972093                       # number of integer regfile reads
system.cpu.int_regfile_writes              1496658984                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  78811105                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 52661052                       # number of floating regfile writes
system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               165988542                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        1470277                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1470276                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback        95971                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        71640                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        71640                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20049                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3159755                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3179804                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       641536                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104183232                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      104824768                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         104824768                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      914915000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      15531000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2359590250                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
system.cpu.icache.tags.replacements              8311                       # number of replacements
system.cpu.icache.tags.tagsinuse          1658.001589                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           394910394                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             10024                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          39396.487829                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1658.001589                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.809571                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.809571                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    394910394                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       394910394                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     394910394                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        394910394                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    394910394                       # number of overall hits
system.cpu.icache.overall_hits::total       394910394                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        12943                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         12943                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        12943                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          12943                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        12943                       # number of overall misses
system.cpu.icache.overall_misses::total         12943                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    383675499                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    383675499                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    383675499                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    383675499                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    383675499                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    383675499                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    394923337                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    394923337                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    394923337                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    394923337                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    394923337                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    394923337                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000033                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000033                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000033                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000033                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000033                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000033                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29643.475160                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 29643.475160                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29643.475160                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 29643.475160                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29643.475160                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 29643.475160                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          706                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    54.307692                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2918                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2918                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2918                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2918                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2918                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2918                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10025                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        10025                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        10025                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        10025                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        10025                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        10025                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281680749                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    281680749                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281680749                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    281680749                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281680749                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    281680749                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28097.830324                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28097.830324                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28097.830324                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 28097.830324                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28097.830324                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28097.830324                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           443340                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32689.012035                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1090033                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           476076                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.289620                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  1332.840421                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    35.208896                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31320.962718                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.040675                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001074                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.955840                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.997589                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst         7273                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1053738                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1061011                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks        95971                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total        95971                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4787                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4787                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         7273                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1058525                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1065798                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         7273                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1058525                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1065798                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2752                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       406514                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       409266                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66853                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66853                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2752                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       473367                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        476119                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2752                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       473367                       # number of overall misses
system.cpu.l2cache.overall_misses::total       476119                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    198914750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  29323124000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  29522038750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5227072250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5227072250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    198914750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  34550196250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  34749111000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    198914750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  34550196250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  34749111000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        10025                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1460252                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1470277                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks        95971                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total        95971                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        71640                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        71640                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        10025                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1531892                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1541917                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        10025                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1531892                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1541917                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.274514                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.278386                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.278360                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.933180                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.933180                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.274514                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.309008                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.308784                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.274514                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.309008                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.308784                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72280.069041                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72133.122106                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.110212                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78187.549549                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78187.549549                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72280.069041                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72988.180946                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72984.088012                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72280.069041                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72988.180946                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72984.088012                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66908                       # number of writebacks
system.cpu.l2cache.writebacks::total            66908                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2752                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406514                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       409266                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66853                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66853                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2752                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       473367                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       476119                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2752                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       473367                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       476119                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    164199250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  24183867000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  24348066250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4422430250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4422430250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    164199250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  28606297250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  28770496500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    164199250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  28606297250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  28770496500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.274514                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278386                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.278360                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.933180                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.933180                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.274514                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.309008                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.308784                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.274514                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.309008                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.308784                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59665.425145                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59490.858863                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.032688                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66151.560139                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66151.560139                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59665.425145                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60431.540961                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.112760                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59665.425145                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60431.540961                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.112760                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1527796                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4094.588575                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           667945835                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1531892                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            436.026714                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         408904250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4094.588575                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999655                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999655                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    458212871                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       458212871                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    209732941                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      209732941                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           23                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           23                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data     667945812                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        667945812                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    667945812                       # number of overall hits
system.cpu.dcache.overall_hits::total       667945812                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1925756                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1925756                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1061955                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1061955                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2987711                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2987711                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2987711                       # number of overall misses
system.cpu.dcache.overall_misses::total       2987711                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  77391156750                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  77391156750                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  46191877602                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  46191877602                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        78000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total        78000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 123583034352                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 123583034352                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 123583034352                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 123583034352                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    460138627                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    460138627                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           24                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           24                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    670933523                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    670933523                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    670933523                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    670933523                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004185                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004185                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005038                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.005038                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.041667                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.041667                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.004453                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.004453                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.004453                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.004453                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.415618                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.415618                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.019744                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.019744                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        78000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        78000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41363.784634                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41363.784634                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41363.784634                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        17901                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          132                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               338                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    52.961538                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          132                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        95971                       # number of writebacks
system.cpu.dcache.writebacks::total             95971                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       465505                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       465505                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       990315                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       990315                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1455820                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1455820                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1455820                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1455820                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460251                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1460251                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71640                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        71640                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1531891                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1531891                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1531891                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1531891                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  41321289000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  41321289000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5347166250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5347166250                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        76000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        76000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46668455250                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  46668455250                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46668455250                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  46668455250                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003174                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003174                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000340                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000340                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041667                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041667                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002283                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002283                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002283                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002283                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28297.387915                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28297.387915                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74639.394891                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74639.394891                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        76000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        76000                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30464.605674                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30464.605674                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30464.605674                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30464.605674                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------