path: root/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.635929                       # Number of seconds simulated
sim_ticks                                635929494500                       # Number of ticks simulated
final_tick                               635929494500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 162504                       # Simulator instruction rate (inst/s)
host_op_rate                                   162504                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               56685894                       # Simulator tick rate (ticks/s)
host_mem_usage                                 228544                       # Number of bytes of host memory used
host_seconds                                 11218.48                       # Real time elapsed on the host
sim_insts                                  1823043370                       # Number of instructions simulated
sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            176704                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          30295616                       # Number of bytes read from this memory
system.physmem.bytes_read::total             30472320                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       176704                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          176704                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4282112                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4282112                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2761                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             473369                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                476130                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66908                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66908                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               277867                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             47639898                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                47917765                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          277867                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             277867                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           6733627                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6733627                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           6733627                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              277867                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            47639898                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54651392                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        476130                       # Number of read requests accepted
system.physmem.writeReqs                        66908                       # Number of write requests accepted
system.physmem.readBursts                      476130                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66908                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 30454144                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     18176                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4280960                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  30472320                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4282112                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      284                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               29443                       # Per bank write bursts
system.physmem.perBankRdBursts::1               29787                       # Per bank write bursts
system.physmem.perBankRdBursts::2               29841                       # Per bank write bursts
system.physmem.perBankRdBursts::3               29778                       # Per bank write bursts
system.physmem.perBankRdBursts::4               29678                       # Per bank write bursts
system.physmem.perBankRdBursts::5               29749                       # Per bank write bursts
system.physmem.perBankRdBursts::6               29855                       # Per bank write bursts
system.physmem.perBankRdBursts::7               29842                       # Per bank write bursts
system.physmem.perBankRdBursts::8               29764                       # Per bank write bursts
system.physmem.perBankRdBursts::9               29879                       # Per bank write bursts
system.physmem.perBankRdBursts::10              29841                       # Per bank write bursts
system.physmem.perBankRdBursts::11              29912                       # Per bank write bursts
system.physmem.perBankRdBursts::12              29773                       # Per bank write bursts
system.physmem.perBankRdBursts::13              29578                       # Per bank write bursts
system.physmem.perBankRdBursts::14              29495                       # Per bank write bursts
system.physmem.perBankRdBursts::15              29631                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4160                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4142                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4099                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4334                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4230                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    635929412000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  476130                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66908                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    408324                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     66857                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       507                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2734                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4071                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4133                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5069                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4046                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4084                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4071                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4061                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4059                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4053                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4045                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4045                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4054                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4045                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       185909                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      186.826200                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     134.409449                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     215.527814                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          65070     35.00%     35.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        87777     47.22%     82.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        21119     11.36%     93.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          448      0.24%     93.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          430      0.23%     94.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          462      0.25%     94.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          533      0.29%     94.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          575      0.31%     94.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         9495      5.11%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         185909                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4044                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean       117.004698                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       36.982691                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     1132.774880                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047           4024     99.51%     99.51% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-6143            1      0.02%     99.53% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-14335            3      0.07%     99.60% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-16383           15      0.37%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::32768-34815            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4044                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4044                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.540554                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.517518                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.888872                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               2948     72.90%     72.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 11      0.27%     73.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18               1080     26.71%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                  5      0.12%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4044                       # Writes before turning the bus around for reads
system.physmem.totQLat                     4824243250                       # Total ticks spent queuing
system.physmem.totMemAccLat               13746355750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2379230000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10138.24                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28888.24                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          47.89                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           6.73                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       47.92                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        6.73                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.37                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.41                       # Average write queue length when enqueuing
system.physmem.readRowHits                     306274                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     50544                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   64.36                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.54                       # Row buffer hit rate for writes
system.physmem.avgGap                      1171058.77                       # Average gap between requests
system.physmem.pageHitRate                      65.74                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     176454220250                       # Time in different power states
system.physmem.memoryStateTime::REF       21234980000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      438237480500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     54651392                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              409276                       # Transaction distribution
system.membus.trans_dist::ReadResp             409276                       # Transaction distribution
system.membus.trans_dist::Writeback             66908                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66854                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66854                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1019168                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1019168                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34754432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            34754432                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               34754432                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1134499000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4452935500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               402497188                       # Number of BP lookups
system.cpu.branchPred.condPredicted         262794086                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          25809520                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            329924346                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               269779526                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             81.770118                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                58338435                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               6772                       # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.read_hits                    522325129                       # DTB read hits
system.cpu.dtb.read_misses                     599769                       # DTB read misses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_accesses                522924898                       # DTB read accesses
system.cpu.dtb.write_hits                   290323928                       # DTB write hits
system.cpu.dtb.write_misses                     50170                       # DTB write misses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_accesses               290374098                       # DTB write accesses
system.cpu.dtb.data_hits                    812649057                       # DTB hits
system.cpu.dtb.data_misses                     649939                       # DTB misses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_accesses                813298996                       # DTB accesses
system.cpu.itb.fetch_hits                   408884134                       # ITB hits
system.cpu.itb.fetch_misses                       679                       # ITB misses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_accesses               408884813                       # ITB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.workload.num_syscalls                   39                       # Number of system calls
system.cpu.numCycles                       1271858990                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          427176335                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     3374139678                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   402497188                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          328117961                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     650903682                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               174116050                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               24391105                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          7638                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           40                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 408884134                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               8158289                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1250296288                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.698672                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.147490                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                599392606     47.94%     47.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 59914511      4.79%     52.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 43339464      3.47%     56.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 76172685      6.09%     62.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                135820925     10.86%     73.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 46245373      3.70%     76.85% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 41570756      3.32%     80.18% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  7626661      0.61%     80.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                240213307     19.21%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1250296288                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.316464                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.652920                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                437590524                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              25041136                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 638845250                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1014076                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              147805302                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             33122555                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 12366                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3318032791                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 46593                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              147805302                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                458553010                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 7909851                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles          27396                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 618894367                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              17106362                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             3208538957                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  6484                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  32278                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               17594215                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                 887362                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          2130246681                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            3706452753                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       3620701555                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          85751197                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1384969070                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                745277611                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               4240                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts            107                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12056800                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            776684532                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           361655801                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          80427234                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         13113632                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2720222433                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded                  90                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2182396478                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          17917271                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       897142134                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    813907304                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved             51                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1250296288                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.745503                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.834496                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           456063276     36.48%     36.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           196937863     15.75%     52.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           246215948     19.69%     71.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           118632312      9.49%     81.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            96039549      7.68%     89.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            85322198      6.82%     95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            31637786      2.53%     98.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            19044967      1.52%     99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              402389      0.03%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1250296288                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1147020      2.84%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               25333961     62.75%     65.59% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              13891524     34.41%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass              2752      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1250439249     57.30%     57.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                17094      0.00%     57.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd            27851471      1.28%     58.57% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp             8254698      0.38%     58.95% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt             7204651      0.33%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.28% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            592678275     27.16%     86.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           295948284     13.56%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2182396478                       # Type of FU issued
system.cpu.iq.rate                           1.715911                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    40372505                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.018499                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         5521594502                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3528574475                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2004997019                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           151784518                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           88865161                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     73949462                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2144972289                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                77793942                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         63261686                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    265614506                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        19945                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        77572                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    150860905                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads         4433                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked          3083                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              147805302                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 7602167                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                279549                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          3087695808                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts             56386                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             776684532                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            361655801                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts                 90                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                 141634                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 84137                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          77572                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       25803318                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect        28659                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             25831977                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2081430874                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             522925034                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts         100965604                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                     367473285                       # number of nop insts executed
system.cpu.iew.exec_refs                    813299641                       # number of memory reference insts executed
system.cpu.iew.exec_branches                277669733                       # Number of branches executed
system.cpu.iew.exec_stores                  290374607                       # Number of stores executed
system.cpu.iew.exec_rate                     1.636526                       # Inst execution rate
system.cpu.iew.wb_sent                     2081298559                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2078946481                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1190563677                       # num instructions producing a value
system.cpu.iew.wb_consumers                1779120207                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.634573                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.669187                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts      1061256381                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          25797472                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1102490986                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.822226                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.529076                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    487378417     44.21%     44.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    227745323     20.66%     64.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    117618714     10.67%     75.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     58023945      5.26%     80.80% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     49786654      4.52%     85.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     22711490      2.06%     87.37% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     18023785      1.63%     89.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     18535022      1.68%     90.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8    102667636      9.31%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1102490986                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           2008987604                       # Number of instructions committed
system.cpu.commit.committedOps             2008987604                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      721864922                       # Number of memory references committed
system.cpu.commit.loads                     511070026                       # Number of loads committed
system.cpu.commit.membars                           0                       # Number of memory barriers committed
system.cpu.commit.branches                  266706457                       # Number of branches committed
system.cpu.commit.fp_insts                   71824891                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1778941351                       # Number of committed integer instructions.
system.cpu.commit.function_calls             39955347                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass    185946986      9.26%      9.26% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu       1058512436     52.69%     61.94% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           15158      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     61.95% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd       27517120      1.37%     63.32% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp        8254514      0.41%     63.73% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt        6876464      0.34%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             4      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     64.07% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       511070026     25.44%     89.51% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      210794896     10.49%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        2008987604                       # Class of committed instruction
system.cpu.commit.bw_lim_events             102667636                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   4064430925                       # The number of ROB reads
system.cpu.rob.rob_writes                  6288295371                       # The number of ROB writes
system.cpu.timesIdled                          345316                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        21562702                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
system.cpu.committedOps                    1823043370                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.697657                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.697657                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.433369                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.433369                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               2650222632                       # number of integer regfile reads
system.cpu.int_regfile_writes              1504597172                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  79149378                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 52661639                       # number of floating regfile writes
system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               164848262                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        1470375                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1470374                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback        95981                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        71643                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        71643                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        20103                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3159913                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3180016                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       643264                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104188608                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      104831872                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         104831872                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      914980500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      15576999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2360120750                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
system.cpu.icache.tags.replacements              8337                       # number of replacements
system.cpu.icache.tags.tagsinuse          1659.365799                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           408871331                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             10051                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          40679.666799                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1659.365799                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.810237                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.810237                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1714                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           74                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1560                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.836914                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         817778319                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        817778319                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    408871331                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       408871331                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     408871331                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        408871331                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    408871331                       # number of overall hits
system.cpu.icache.overall_hits::total       408871331                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        12803                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         12803                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        12803                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          12803                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        12803                       # number of overall misses
system.cpu.icache.overall_misses::total         12803                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    381292998                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    381292998                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    381292998                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    381292998                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    381292998                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    381292998                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    408884134                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    408884134                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    408884134                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    408884134                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    408884134                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    408884134                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000031                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000031                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000031                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000031                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000031                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000031                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29781.535421                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 29781.535421                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29781.535421                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 29781.535421                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29781.535421                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 29781.535421                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          690                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    57.500000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2751                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2751                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2751                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2751                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2751                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2751                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10052                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        10052                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        10052                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        10052                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        10052                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        10052                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281850750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    281850750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281850750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    281850750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281850750                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    281850750                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28039.270792                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28039.270792                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28039.270792                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 28039.270792                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28039.270792                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28039.270792                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           443352                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32689.433900                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1090130                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           476087                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.289771                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  1333.307331                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    35.512650                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31320.613920                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.040689                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001084                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.955829                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.997602                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32735                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          158                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          196                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          501                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4985                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26895                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.998993                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         13651722                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        13651722                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst         7290                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1053808                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1061098                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks        95981                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total        95981                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4789                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4789                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst         7290                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1058597                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1065887                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst         7290                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1058597                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1065887                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2762                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       406515                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       409277                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66854                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66854                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2762                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       473369                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        476131                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2762                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       473369                       # number of overall misses
system.cpu.l2cache.overall_misses::total       476131                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    198889750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  28901614750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  29100504500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5230880500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   5230880500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    198889750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  34132495250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  34331385000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    198889750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  34132495250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  34331385000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        10052                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1460323                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1470375                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks        95981                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total        95981                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        71643                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        71643                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        10052                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1531966                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1542018                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        10052                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1531966                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1542018                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.274771                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.278373                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.278349                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.933155                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.933155                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.274771                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.308994                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.308771                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.274771                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.308994                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.308771                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72009.322954                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71096.059801                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 71102.222944                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78243.343704                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78243.343704                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72009.322954                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72105.472158                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 72104.914404                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72009.322954                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72105.472158                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 72104.914404                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66908                       # number of writebacks
system.cpu.l2cache.writebacks::total            66908                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2762                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406515                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       409277                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66854                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66854                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2762                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       473369                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       476131                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2762                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       473369                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       476131                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    164041750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  23797651250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  23961693000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4425694500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4425694500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    164041750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  28223345750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  28387387500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    164041750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  28223345750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  28387387500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.274771                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.278373                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.278349                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.933155                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.933155                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.274771                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.308994                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.308771                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.274771                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.308994                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.308771                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59392.378711                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58540.647332                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58546.395229                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66199.397194                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66199.397194                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59392.378711                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59622.294130                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59620.960408                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59392.378711                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59622.294130                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59620.960408                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1527870                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4094.609891                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           666862520                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1531966                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            435.298512                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         407274250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4094.609891                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999661                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999661                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          287                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          967                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         2348                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4          409                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1341234178                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1341234178                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    457128371                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       457128371                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    209734126                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      209734126                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           23                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           23                       # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data     666862497                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        666862497                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    666862497                       # number of overall hits
system.cpu.dcache.overall_hits::total       666862497                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1927816                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1927816                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1060770                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1060770                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2988586                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2988586                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2988586                       # number of overall misses
system.cpu.dcache.overall_misses::total       2988586                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  76893359750                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  76893359750                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  46482150765                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  46482150765                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 123375510515                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 123375510515                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 123375510515                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 123375510515                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    459056187                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    459056187                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           23                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           23                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    669851083                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    669851083                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    669851083                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    669851083                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004200                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004200                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005032                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.005032                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.004462                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.004462                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.004462                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.004462                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39886.254575                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 39886.254575                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43819.254659                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 43819.254659                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41282.235316                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41282.235316                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41282.235316                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41282.235316                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs        19699                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          140                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               433                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    45.494226                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          140                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        95981                       # number of writebacks
system.cpu.dcache.writebacks::total             95981                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       467493                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       467493                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       989127                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       989127                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1456620                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1456620                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1456620                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1456620                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460323                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1460323                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71643                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        71643                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1531966                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1531966                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1531966                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1531966                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  40901282750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  40901282750                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5350796500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5350796500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  46252079250                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  46252079250                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  46252079250                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  46252079250                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003181                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003181                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000340                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000340                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002287                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002287                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002287                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002287                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28008.380851                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28008.380851                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74686.940804                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74686.940804                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30191.322294                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30191.322294                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30191.322294                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30191.322294                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------