1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
|
---------- Begin Simulation Statistics ----------
sim_seconds 0.512589 # Number of seconds simulated
sim_ticks 512588680500 # Number of ticks simulated
final_tick 512588680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 180394 # Simulator instruction rate (inst/s)
host_op_rate 222088 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 144333179 # Simulator tick rate (ticks/s)
host_mem_usage 275860 # Number of bytes of host memory used
host_seconds 3551.43 # Real time elapsed on the host
sim_insts 640655085 # Number of instructions simulated
sim_ops 788730744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 18474048 # Number of bytes read from this memory
system.physmem.bytes_read::total 18638208 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 288657 # Number of read requests responded to by this memory
system.physmem.num_reads::total 291222 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 320257 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 36040687 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 36360943 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 320257 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 320257 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 8252761 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 8252761 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 8252761 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 320257 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 36040687 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 44613705 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 291222 # Number of read requests accepted
system.physmem.writeReqs 66098 # Number of write requests accepted
system.physmem.readBursts 291222 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue
system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 18638208 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 18288 # Per bank write bursts
system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
system.physmem.perBankRdBursts::2 18220 # Per bank write bursts
system.physmem.perBankRdBursts::3 18178 # Per bank write bursts
system.physmem.perBankRdBursts::4 18281 # Per bank write bursts
system.physmem.perBankRdBursts::5 18410 # Per bank write bursts
system.physmem.perBankRdBursts::6 18174 # Per bank write bursts
system.physmem.perBankRdBursts::7 17993 # Per bank write bursts
system.physmem.perBankRdBursts::8 18029 # Per bank write bursts
system.physmem.perBankRdBursts::9 18057 # Per bank write bursts
system.physmem.perBankRdBursts::10 18103 # Per bank write bursts
system.physmem.perBankRdBursts::11 18205 # Per bank write bursts
system.physmem.perBankRdBursts::12 18223 # Per bank write bursts
system.physmem.perBankRdBursts::13 18272 # Per bank write bursts
system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
system.physmem.perBankRdBursts::15 18257 # Per bank write bursts
system.physmem.perBankWrBursts::0 4171 # Per bank write bursts
system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
system.physmem.perBankWrBursts::2 4135 # Per bank write bursts
system.physmem.perBankWrBursts::3 4146 # Per bank write bursts
system.physmem.perBankWrBursts::4 4223 # Per bank write bursts
system.physmem.perBankWrBursts::5 4222 # Per bank write bursts
system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 512588586500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 291222 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 290535 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 910 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 910 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 110334 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 207.049577 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 134.865332 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 256.872236 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 45104 40.88% 40.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 43590 39.51% 80.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9238 8.37% 88.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1655 1.50% 90.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 896 0.81% 91.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 605 0.55% 91.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 780 0.71% 92.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 416 0.38% 92.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8050 7.30% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 110334 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4016 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 48.533367 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 34.247557 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 506.662918 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 4014 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4016 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4016 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.453187 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.432732 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.838251 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3107 77.37% 77.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 907 22.58% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4016 # Writes before turning the bus around for reads
system.physmem.totQLat 2758807250 # Total ticks spent queuing
system.physmem.totMemAccLat 8213182250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9483.70 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 28233.70 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 36.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 8.25 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 36.36 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.35 # Data bus utilization in percentage
system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing
system.physmem.readRowHits 195021 # Number of row buffer hits during reads
system.physmem.writeRowHits 51610 # Number of row buffer hits during writes
system.physmem.readRowHitRate 67.04 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.08 # Row buffer hit rate for writes
system.physmem.avgGap 1434536.51 # Average gap between requests
system.physmem.pageHitRate 69.08 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 417312000 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 227700000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1136202600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 215544240 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 103911193800 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 216400632000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 355788106560 # Total energy per rank (pJ)
system.physmem_0.averagePower 694.106023 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 359300376000 # Time in different power states
system.physmem_0.memoryStateTime::REF 17116320000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 136167987750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 416737440 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 227386500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1132435200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 103626578835 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 216650294250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 355745582385 # Total energy per rank (pJ)
system.physmem_1.averagePower 694.023062 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 359717078250 # Time in different power states
system.physmem_1.memoryStateTime::REF 17116320000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 135751825750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups 147261658 # Number of BP lookups
system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups
system.cpu.branchPred.BTBHits 63294628 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
system.cpu.pwrStateResidencyTicks::ON 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 1025177361 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 640655085 # Number of instructions committed
system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed
system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.600202 # CPI: cycles per instruction
system.cpu.ipc 0.624921 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction
system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction
system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 788730744 # Class of committed instruction
system.cpu.tickCycles 955908039 # Number of cycles that the object actually ticked
system.cpu.idleCycles 69269322 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 778100 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.241926 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 798177500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.241926 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999083 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999083 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1420 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 378434445 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 378434445 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 378437929 # number of overall hits
system.cpu.dcache.overall_hits::total 378437929 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 850904 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses
system.cpu.dcache.overall_misses::total 851045 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24628452500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24628452500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10137526000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10137526000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 34765978500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 34765978500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 34765978500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 34765978500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 379285349 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 379285349 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 379288974 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 379288974 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002849 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002849 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34532.709986 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34532.709986 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73613.962472 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73613.962472 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40857.697813 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40857.697813 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40850.928564 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40850.928564 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 88716 # number of writebacks
system.cpu.dcache.writebacks::total 88716 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 68847 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 68847 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 68847 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 68847 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712735 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 712735 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 782057 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23907337500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23907337500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084282000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084282000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28991619500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 28991619500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993407500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28993407500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33543.094558 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33543.094558 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73342.979141 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73342.979141 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37070.980120 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37070.980120 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37066.678301 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37066.678301 # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 24885 # number of replacements
system.cpu.icache.tags.tagsinuse 1711.979735 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 257789647 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 9678.241741 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1711.979735 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.835928 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.835928 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 515659204 # Number of tag accesses
system.cpu.icache.tags.data_accesses 515659204 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 257789647 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 257789647 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 257789647 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 257789647 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 257789647 # number of overall hits
system.cpu.icache.overall_hits::total 257789647 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses
system.cpu.icache.overall_misses::total 26637 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 515552500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 515552500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 515552500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 515552500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 515552500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 515552500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 257816284 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 257816284 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 257816284 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 257816284 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 257816284 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 257816284 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19354.750910 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19354.750910 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19354.750910 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19354.750910 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 24885 # number of writebacks
system.cpu.icache.writebacks::total 24885 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26637 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 26637 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 26637 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 488916500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 488916500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 488916500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 488916500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 488916500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 488916500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18354.788452 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18354.788452 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 258816 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32567.443571 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1247529 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 291562 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.278778 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 2619.708679 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.014636 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29858.720256 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.079947 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002717 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.911216 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29128 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 13229556 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 13229556 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks 88716 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 88716 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490282 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 490282 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 24067 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 493513 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 517580 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 24067 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 493513 # number of overall hits
system.cpu.l2cache.overall_hits::total 517580 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2570 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2570 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222592 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 222592 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 288683 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 291253 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 288683 # number of overall misses
system.cpu.l2cache.overall_misses::total 291253 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4946370000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4946370000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194980000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 194980000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17689881000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17689881000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 194980000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22636251000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22831231000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 194980000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22636251000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22831231000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88716 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 88716 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26637 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 26637 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712874 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 712874 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 26637 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 782196 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 808833 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 26637 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 782196 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 808833 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096482 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096482 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312246 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312246 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.369067 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.360090 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.369067 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.360090 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74841.809021 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74841.809021 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.704280 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.704280 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79472.222721 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79472.222721 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78389.685256 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78389.685256 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 26 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 26 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222566 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222566 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 288657 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 291223 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 288657 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 291223 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285460000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285460000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169076000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169076000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15462440500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15462440500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169076000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19747900500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19916976500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169076000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19747900500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19916976500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312209 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312209 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.360053 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.360053 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64841.809021 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64841.809021 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65890.880748 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65890.880748 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69473.506735 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69473.506735 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 154814 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 882102 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78158 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55738368 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 59035712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 258816 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1067649 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.004997 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.070711 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 1062329 99.50% 99.50% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 5305 0.50% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1067649 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 919510000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 225131 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
system.membus.trans_dist::CleanEvict 190690 # Transaction distribution
system.membus.trans_dist::ReadExReq 66091 # Transaction distribution
system.membus.trans_dist::ReadExResp 66091 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 225131 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839232 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 839232 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22868480 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 548010 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 548010 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 548010 # Request fanout histogram
system.membus.reqLayer0.occupancy 917220500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 1554785500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
|