path: root/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.541068                       # Number of seconds simulated
sim_ticks                                541067717500                       # Number of ticks simulated
final_tick                               541067717500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 180313                       # Simulator instruction rate (inst/s)
host_op_rate                                   221989                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              152283805                       # Simulator tick rate (ticks/s)
host_mem_usage                                 322972                       # Number of bytes of host memory used
host_seconds                                  3553.02                       # Real time elapsed on the host
sim_insts                                   640655085                       # Number of instructions simulated
sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            164736                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          18470272                       # Number of bytes read from this memory
system.physmem.bytes_read::total             18635008                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       164736                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          164736                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2574                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             288598                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                291172                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               304465                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             34136710                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                34441175                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          304465                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             304465                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           7818378                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                7818378                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           7818378                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              304465                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            34136710                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               42259553                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        291172                       # Number of read requests accepted
system.physmem.writeReqs                        66098                       # Number of write requests accepted
system.physmem.readBursts                      291172                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 18613824                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     21184                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4228224                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  18635008                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      331                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               18282                       # Per bank write bursts
system.physmem.perBankRdBursts::1               18127                       # Per bank write bursts
system.physmem.perBankRdBursts::2               18214                       # Per bank write bursts
system.physmem.perBankRdBursts::3               18173                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18274                       # Per bank write bursts
system.physmem.perBankRdBursts::5               18402                       # Per bank write bursts
system.physmem.perBankRdBursts::6               18180                       # Per bank write bursts
system.physmem.perBankRdBursts::7               17989                       # Per bank write bursts
system.physmem.perBankRdBursts::8               18022                       # Per bank write bursts
system.physmem.perBankRdBursts::9               18061                       # Per bank write bursts
system.physmem.perBankRdBursts::10              18102                       # Per bank write bursts
system.physmem.perBankRdBursts::11              18198                       # Per bank write bursts
system.physmem.perBankRdBursts::12              18215                       # Per bank write bursts
system.physmem.perBankRdBursts::13              18265                       # Per bank write bursts
system.physmem.perBankRdBursts::14              18078                       # Per bank write bursts
system.physmem.perBankRdBursts::15              18259                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4098                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4092                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4093                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4095                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4095                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    541067624000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  291172                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    290452                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       372                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4014                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4020                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4020                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       110882                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      205.996862                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     134.129754                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     256.860056                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          45611     41.13%     41.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        43911     39.60%     80.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         9208      8.30%     89.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1504      1.36%     90.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          772      0.70%     91.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          428      0.39%     91.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          846      0.76%     92.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          594      0.54%     92.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8008      7.22%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         110882                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4017                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        48.509335                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       34.234035                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      506.719748                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           4015     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4017                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4017                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.446602                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.426400                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.833021                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3120     77.67%     77.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                897     22.33%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4017                       # Writes before turning the bus around for reads
system.physmem.totQLat                     3065169000                       # Total ticks spent queuing
system.physmem.totMemAccLat                8518437750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1454205000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       10538.99                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  29288.99                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          34.40                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           7.81                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       34.44                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        7.82                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        28.63                       # Average write queue length when enqueuing
system.physmem.readRowHits                     194425                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     51597                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   66.85                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.06                       # Row buffer hit rate for writes
system.physmem.avgGap                      1514450.20                       # Average gap between requests
system.physmem.pageHitRate                      68.93                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  420041160                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  229189125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1135976400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                215531280                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            35339834400                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           108869403780                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           229140586500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             375350562645                       # Total energy per rank (pJ)
system.physmem_0.averagePower              693.723181                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   380482098250                       # Time in different power states
system.physmem_0.memoryStateTime::REF     18067400000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    142518050750                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  418226760                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  228199125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1132497600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                212576400                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            35339834400                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           107776907010                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           230098917000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             375207158295                       # Total energy per rank (pJ)
system.physmem_1.averagePower              693.458141                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   382081982750                       # Time in different power states
system.physmem_1.memoryStateTime::REF     18067400000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    140917403500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               157565509                       # Number of BP lookups
system.cpu.branchPred.condPredicted         107229273                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12892751                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             98103751                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                81778311                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             83.359005                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                19318729                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               1315                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  673                       # Number of system calls
system.cpu.numCycles                       1082135435                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   640655085                       # Number of instructions committed
system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      23942424                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.689108                       # CPI: cycles per instruction
system.cpu.ipc                               0.592029                       # IPC: instructions per cycle
system.cpu.tickCycles                      1024380125                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        57755310                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            778330                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4092.458630                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           378454621                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            782426                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            483.693820                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         795587500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4092.458630                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999135                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999135                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          964                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         1346                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1586                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         759395078                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        759395078                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    249625893                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       249625893                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      128813765                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         3485                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          3485                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     378439658                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        378439658                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    378443143                       # number of overall hits
system.cpu.dcache.overall_hits::total       378443143                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       713852                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        713852                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       137712                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       137712                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          141                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          141                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data       851564                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         851564                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       851705                       # number of overall misses
system.cpu.dcache.overall_misses::total        851705                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  24973506500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  24973506500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10064105500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10064105500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35037612000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35037612000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35037612000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35037612000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    250339745                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    250339745                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         3626                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         3626                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    379291222                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    379291222                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    379294848                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    379294848                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002852                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002852                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001068                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001068                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038886                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.038886                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002245                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002245                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002245                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34984.151477                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34984.151477                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73080.817213                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73080.817213                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41145.013176                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41145.013176                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41138.201607                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41138.201607                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        88940                       # number of writebacks
system.cpu.dcache.writebacks::total             88940                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          887                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          887                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68390                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        68390                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        69277                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        69277                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        69277                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        69277                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712965                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       712965                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69322                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       782287                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       782287                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       782426                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       782426                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24245308500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  24245308500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5047418500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5047418500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1788000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1788000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29292727000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  29292727000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29294515000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  29294515000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002848                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038334                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038334                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34006.309566                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34006.309566                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72811.207120                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72811.207120                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37444.987581                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37444.987581                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37440.620583                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37440.620583                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             23593                       # number of replacements
system.cpu.icache.tags.tagsinuse          1712.048816                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           288484492                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             25344                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          11382.752999                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1712.048816                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.835961                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.835961                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1603                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         577045018                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        577045018                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    288484492                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       288484492                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     288484492                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        288484492                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    288484492                       # number of overall hits
system.cpu.icache.overall_hits::total       288484492                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        25345                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         25345                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        25345                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          25345                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        25345                       # number of overall misses
system.cpu.icache.overall_misses::total         25345                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    499936000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    499936000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    499936000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    499936000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    499936000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    499936000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    288509837                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    288509837                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    288509837                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    288509837                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    288509837                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    288509837                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000088                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000088                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000088                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000088                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000088                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000088                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19725.231801                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19725.231801                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19725.231801                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19725.231801                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19725.231801                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19725.231801                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25345                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        25345                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        25345                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        25345                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        25345                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        25345                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    474592000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    474592000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    474592000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    474592000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    474592000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    474592000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000088                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000088                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000088                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000088                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000088                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000088                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18725.271257                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18725.271257                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18725.271257                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18725.271257                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18725.271257                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18725.271257                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           258392                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32574.171271                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1245331                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           291136                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.277489                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  2589.797972                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    90.410409                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29893.962890                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.079034                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002759                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.912291                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.994085                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          148                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2812                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29416                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         13211274                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        13211274                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks        88940                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total        88940                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         3231                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         3231                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        22766                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        22766                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490569                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       490569                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        22766                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       493800                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          516566                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        22766                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       493800                       # number of overall hits
system.cpu.l2cache.overall_hits::total         516566                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data        66091                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66091                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2579                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2579                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222535                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       222535                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2579                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       288626                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        291205                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2579                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       288626                       # number of overall misses
system.cpu.l2cache.overall_misses::total       291205                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4909508000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   4909508000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    197530500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    197530500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18026385000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  18026385000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    197530500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  22935893000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  23133423500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    197530500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  22935893000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  23133423500                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks        88940                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total        88940                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        69322                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        69322                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        25345                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        25345                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       713104                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       713104                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        25345                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       782426                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       807771                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        25345                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       782426                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       807771                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953391                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.953391                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.101756                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.101756                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312065                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312065                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.101756                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.368886                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.360504                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.101756                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.368886                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.360504                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74284.062883                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74284.062883                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76591.896084                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76591.896084                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81004.718359                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81004.718359                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76591.896084                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79465.789638                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79440.337563                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76591.896084                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79465.789638                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79440.337563                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            4                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            4                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           28                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           28                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           28                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           32                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           28                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           32                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          369                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total          369                       # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66091                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66091                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2575                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2575                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222507                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222507                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2575                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       288598                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       291173                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2575                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       288598                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       291173                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4248598000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4248598000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    171535500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    171535500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15799227000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15799227000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171535500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20047825000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  20219360500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171535500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20047825000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  20219360500                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.101598                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.101598                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312026                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312026                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.101598                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368850                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.360465                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.101598                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368850                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.360465                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64284.062883                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64284.062883                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66615.728155                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66615.728155                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71005.527916                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71005.527916                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66615.728155                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69466.264492                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69441.055661                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66615.728155                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69466.264492                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69441.055661                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp        738448                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       155038                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       901935                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        25345                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       713104                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        72953                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2341169                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2414122                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1622016                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55767424                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           57389440                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      258392                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1868086                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.138319                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.345235                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            1609694     86.17%     86.17% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             258392     13.83%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1868086                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      893787000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      38017996                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1173652972                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             225081                       # Transaction distribution
system.membus.trans_dist::Writeback             66098                       # Transaction distribution
system.membus.trans_dist::CleanEvict           190637                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        225081                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839079                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 839079                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22865280                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22865280                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            547907                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  547907    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              547907                       # Request fanout histogram
system.membus.reqLayer0.occupancy           916769500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1554235250                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------