path: root/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.545048                       # Number of seconds simulated
sim_ticks                                545048444500                       # Number of ticks simulated
final_tick                               545048444500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 177094                       # Simulator instruction rate (inst/s)
host_op_rate                                   218026                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              150665678                       # Simulator tick rate (ticks/s)
host_mem_usage                                 323140                       # Number of bytes of host memory used
host_seconds                                  3617.60                       # Real time elapsed on the host
sim_insts                                   640655085                       # Number of instructions simulated
sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            164544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          18429312                       # Number of bytes read from this memory
system.physmem.bytes_read::total             18593856                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       164544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          164544                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2571                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             287958                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                290529                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               301889                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             33812246                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                34114135                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          301889                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             301889                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           7761277                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                7761277                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           7761277                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              301889                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            33812246                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               41875412                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        290529                       # Number of read requests accepted
system.physmem.writeReqs                        66098                       # Number of write requests accepted
system.physmem.readBursts                      290529                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 18574016                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     19840                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4228992                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  18593856                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      310                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               18284                       # Per bank write bursts
system.physmem.perBankRdBursts::1               18137                       # Per bank write bursts
system.physmem.perBankRdBursts::2               18223                       # Per bank write bursts
system.physmem.perBankRdBursts::3               18185                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18266                       # Per bank write bursts
system.physmem.perBankRdBursts::5               18315                       # Per bank write bursts
system.physmem.perBankRdBursts::6               18094                       # Per bank write bursts
system.physmem.perBankRdBursts::7               17909                       # Per bank write bursts
system.physmem.perBankRdBursts::8               17941                       # Per bank write bursts
system.physmem.perBankRdBursts::9               17963                       # Per bank write bursts
system.physmem.perBankRdBursts::10              18019                       # Per bank write bursts
system.physmem.perBankRdBursts::11              18118                       # Per bank write bursts
system.physmem.perBankRdBursts::12              18147                       # Per bank write bursts
system.physmem.perBankRdBursts::13              18275                       # Per bank write bursts
system.physmem.perBankRdBursts::14              18077                       # Per bank write bursts
system.physmem.perBankRdBursts::15              18266                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4102                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4147                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4226                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4225                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4171                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4095                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4090                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4090                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4140                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    545048350000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  290529                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    289827                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       376                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      967                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4010                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       112309                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      203.026151                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     132.211216                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     254.422571                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          47277     42.10%     42.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        43772     38.97%     81.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         8960      7.98%     89.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1911      1.70%     90.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          490      0.44%     91.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          736      0.66%     91.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          729      0.65%     92.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          499      0.44%     92.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         7935      7.07%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         112309                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4009                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        48.524570                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       36.056534                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      507.518625                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           4006     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4009                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4009                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.482415                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.461068                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.856030                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3042     75.88%     75.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  1      0.02%     75.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                965     24.07%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4009                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2724193250                       # Total ticks spent queuing
system.physmem.totMemAccLat                8165799500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1451095000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                        9386.68                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  28136.68                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          34.08                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           7.76                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       34.11                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        7.76                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        21.79                       # Average write queue length when enqueuing
system.physmem.readRowHits                     193908                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     50072                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   66.81                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.75                       # Row buffer hit rate for writes
system.physmem.avgGap                      1528342.92                       # Average gap between requests
system.physmem.pageHitRate                      68.47                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  423889200                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  231288750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1134182400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                215628480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            35599708560                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           106422668235                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           233674110000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             377701475625                       # Total energy per rank (pJ)
system.physmem_0.averagePower              692.972318                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   388027097500                       # Time in different power states
system.physmem_0.memoryStateTime::REF     18200260000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    138818528500                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  425113920                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  231957000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1129245000                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                212556960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            35599708560                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           106328346345                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           233756848500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             377683776285                       # Total energy per rank (pJ)
system.physmem_1.averagePower              692.939845                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   388162097500                       # Time in different power states
system.physmem_1.memoryStateTime::REF     18200260000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    138683202500                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               155052076                       # Number of BP lookups
system.cpu.branchPred.condPredicted         105344550                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12879569                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             90401009                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                82966187                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             91.775731                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                19284792                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               1316                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  673                       # Number of system calls
system.cpu.numCycles                       1090096889                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   640655085                       # Number of instructions committed
system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                      22623818                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.701535                       # CPI: cycles per instruction
system.cpu.ipc                               0.587705                       # IPC: instructions per cycle
system.cpu.tickCycles                      1030366439                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        59730450                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            778156                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4092.460333                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           378456871                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            782252                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            483.804287                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         802330000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4092.460333                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999136                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999136                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          172                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          962                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         1339                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1593                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         759399046                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        759399046                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    249628143                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       249628143                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      128813765                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         3485                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          3485                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     378441908                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        378441908                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    378445393                       # number of overall hits
system.cpu.dcache.overall_hits::total       378445393                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       713673                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        713673                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       137712                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       137712                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          141                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          141                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data       851385                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         851385                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       851526                       # number of overall misses
system.cpu.dcache.overall_misses::total        851526                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  24678796218                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  24678796218                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10203720250                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10203720250                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  34882516468                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  34882516468                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  34882516468                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  34882516468                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    250341816                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    250341816                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         3626                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         3626                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    379293293                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    379293293                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    379296919                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    379296919                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002851                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002851                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001068                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001068                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038886                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.038886                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002245                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002245                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002245                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34579.977410                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34579.977410                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74094.634091                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 74094.634091                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40971.495232                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40971.495232                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40964.710964                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40964.710964                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        91420                       # number of writebacks
system.cpu.dcache.writebacks::total             91420                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          882                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          882                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68390                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        68390                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        69272                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        69272                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        69272                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        69272                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712791                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       712791                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69322                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       782113                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       782113                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       782252                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       782252                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23523501277                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  23523501277                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5052240750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5052240750                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1719000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1719000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28575742027                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  28575742027                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28577461027                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  28577461027                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002847                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002847                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038334                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038334                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002062                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33001.961693                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33001.961693                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72880.770174                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72880.770174                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36536.590016                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36536.590016                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36532.295254                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 36532.295254                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             23595                       # number of replacements
system.cpu.icache.tags.tagsinuse          1710.136306                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           292011682                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             25344                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          11521.925584                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1710.136306                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.835027                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.835027                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           92                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1601                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.854004                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         584099398                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        584099398                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    292011682                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       292011682                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     292011682                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        292011682                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    292011682                       # number of overall hits
system.cpu.icache.overall_hits::total       292011682                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        25345                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         25345                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        25345                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          25345                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        25345                       # number of overall misses
system.cpu.icache.overall_misses::total         25345                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    498945745                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    498945745                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    498945745                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    498945745                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    498945745                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    498945745                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    292037027                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    292037027                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    292037027                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    292037027                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    292037027                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    292037027                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000087                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000087                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19686.160781                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19686.160781                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19686.160781                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19686.160781                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19686.160781                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19686.160781                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25345                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        25345                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        25345                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        25345                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        25345                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        25345                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    459825255                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    459825255                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    459825255                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    459825255                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    459825255                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    459825255                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18142.641744                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18142.641744                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18142.641744                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18142.641744                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18142.641744                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18142.641744                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           257749                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32573.780035                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             539008                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           290493                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             1.855494                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  2882.224162                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    89.373270                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29602.182603                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.087959                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002727                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.903387                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.994073                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2792                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29435                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          7551951                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         7551951                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        22768                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       491036                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         513804                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks        91420                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total        91420                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         3231                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         3231                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        22768                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       494267                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          517035                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        22768                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       494267                       # number of overall hits
system.cpu.l2cache.overall_hits::total         517035                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2577                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       221894                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       224471                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66091                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66091                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2577                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       287985                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        290562                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2577                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       287985                       # number of overall misses
system.cpu.l2cache.overall_misses::total       290562                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    195416750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17656346250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  17851763000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4948991250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   4948991250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    195416750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  22605337500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  22800754250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    195416750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  22605337500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  22800754250                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        25345                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       712930                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       738275                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks        91420                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total        91420                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        69322                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        69322                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        25345                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       782252                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       807597                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        25345                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       782252                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       807597                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.101677                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.311242                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.304048                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953391                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.953391                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.101677                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.368149                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.359786                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.101677                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.368149                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.359786                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75831.102057                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79571.084617                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79528.148402                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74881.470246                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74881.470246                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75831.102057                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78494.843481                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78471.218707                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75831.102057                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78494.843481                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78471.218707                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            5                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           27                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           32                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           27                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           32                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           27                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           32                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2572                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       221867                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       224439                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66091                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66091                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2572                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       287958                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       290530                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2572                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       287958                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       290530                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    162876000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  14878894250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  15041770250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4120650250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4120650250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    162876000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  18999544500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  19162420500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    162876000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  18999544500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  19162420500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.101480                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.311204                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.304005                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.101480                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368114                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.359746                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.101480                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368114                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.359746                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63326.594090                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67062.223089                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67019.413961                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62348.129851                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62348.129851                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63326.594090                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65980.262747                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65956.770385                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63326.594090                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65980.262747                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65956.770385                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         738275                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        738274                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback        91420                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        50689                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1655924                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           1706613                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1622016                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55915008                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           57537024                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples       899017                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean               1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             899017    100.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         899017                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      540928500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      38568245                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1224009973                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
system.membus.trans_dist::ReadReq              224438                       # Transaction distribution
system.membus.trans_dist::ReadResp             224438                       # Transaction distribution
system.membus.trans_dist::Writeback             66098                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       647156                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 647156                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22824128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22824128                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            356627                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  356627    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              356627                       # Request fanout histogram
system.membus.reqLayer0.occupancy           732101500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1551130500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------