path: root/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.409388                       # Number of seconds simulated
sim_ticks                                409388341000                       # Number of ticks simulated
final_tick                               409388341000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  75979                       # Simulator instruction rate (inst/s)
host_op_rate                                    93540                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               48552243                       # Simulator tick rate (ticks/s)
host_mem_usage                                 312124                       # Number of bytes of host memory used
host_seconds                                  8431.91                       # Real time elapsed on the host
sim_insts                                   640649299                       # Number of instructions simulated
sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            226496                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7024000                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     12938624                       # Number of bytes read from this memory
system.physmem.bytes_read::total             20189120                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       226496                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          226496                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4245888                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4245888                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3539                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             109750                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       202166                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                315455                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66342                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66342                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               553255                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             17157303                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     31604769                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                49315327                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          553255                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             553255                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          10371297                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               10371297                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          10371297                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              553255                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            17157303                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     31604769                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               59686624                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        315455                       # Number of read requests accepted
system.physmem.writeReqs                        66342                       # Number of write requests accepted
system.physmem.readBursts                      315455                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66342                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 20169536                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     19584                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4238784                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  20189120                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4245888                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      306                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      81                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             18                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               19899                       # Per bank write bursts
system.physmem.perBankRdBursts::1               19575                       # Per bank write bursts
system.physmem.perBankRdBursts::2               19715                       # Per bank write bursts
system.physmem.perBankRdBursts::3               19833                       # Per bank write bursts
system.physmem.perBankRdBursts::4               19635                       # Per bank write bursts
system.physmem.perBankRdBursts::5               20130                       # Per bank write bursts
system.physmem.perBankRdBursts::6               19631                       # Per bank write bursts
system.physmem.perBankRdBursts::7               19419                       # Per bank write bursts
system.physmem.perBankRdBursts::8               19547                       # Per bank write bursts
system.physmem.perBankRdBursts::9               19463                       # Per bank write bursts
system.physmem.perBankRdBursts::10              19540                       # Per bank write bursts
system.physmem.perBankRdBursts::11              19765                       # Per bank write bursts
system.physmem.perBankRdBursts::12              19604                       # Per bank write bursts
system.physmem.perBankRdBursts::13              19959                       # Per bank write bursts
system.physmem.perBankRdBursts::14              19457                       # Per bank write bursts
system.physmem.perBankRdBursts::15              19977                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4260                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4107                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4142                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4156                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4244                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4228                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4095                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4150                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    409388286500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  315455                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66342                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    122393                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    117234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     14139                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      6795                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6485                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      7459                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      8460                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      8297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     10473                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4424                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     3291                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2480                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1879                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1340                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      583                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      594                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                      991                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1792                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2650                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3281                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3720                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4073                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5046                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5138                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5067                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4379                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4077                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       97                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       87                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       52                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       136711                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      178.525503                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     128.653130                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     198.190580                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          54126     39.59%     39.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        57416     42.00%     81.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        14736     10.78%     92.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1353      0.99%     93.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1490      1.09%     94.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1455      1.06%     95.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1216      0.89%     96.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1169      0.86%     97.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3750      2.74%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         136711                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4038                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        65.701585                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       34.708310                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      449.952316                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            3996     98.96%     98.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023           21      0.52%     99.48% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            8      0.20%     99.68% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047            4      0.10%     99.78% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-3071            1      0.02%     99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-3583            1      0.02%     99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-4607            1      0.02%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119            1      0.02%     99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-5631            1      0.02%     99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239            1      0.02%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-14847            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15872-16383            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4038                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4038                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.401932                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.368431                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.138933                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3429     84.92%     84.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  6      0.15%     85.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                436     10.80%     95.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 81      2.01%     97.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 33      0.82%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 20      0.50%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 10      0.25%     99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  9      0.22%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  1      0.02%     99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  2      0.05%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  6      0.15%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  2      0.05%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  2      0.05%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4038                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9474891317                       # Total ticks spent queuing
system.physmem.totMemAccLat               15383935067                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1575745000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       30064.80                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  48814.80                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          49.27                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          10.35                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       49.32                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       10.37                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.47                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.08                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.56                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.70                       # Average write queue length when enqueuing
system.physmem.readRowHits                     218193                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     26465                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   69.23                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  39.94                       # Row buffer hit rate for writes
system.physmem.avgGap                      1072266.90                       # Average gap between requests
system.physmem.pageHitRate                      64.15                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  518729400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  283036875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1231058400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                216470880                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            26739067680                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            96374211480                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           161092645500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             286455220215                       # Total energy per rank (pJ)
system.physmem_0.averagePower              699.719632                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   267357168520                       # Time in different power states
system.physmem_0.memoryStateTime::REF     13670280000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    128358277730                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  514715040                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  280846500                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1226721600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                212706000                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            26739067680                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            96210213075                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           161236503750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             286420773645                       # Total energy per rank (pJ)
system.physmem_1.averagePower              699.635490                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   267598080337                       # Time in different power states
system.physmem_1.memoryStateTime::REF     13670280000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    128117581163                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               233960254                       # Number of BP lookups
system.cpu.branchPred.condPredicted         161822373                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          15514618                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            121575796                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               108259792                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             89.047159                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                25036830                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1300193                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  673                       # Number of system calls
system.cpu.numCycles                        818776683                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           84080283                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1200690611                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   233960254                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          133296622                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     718833631                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                31063665                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 2156                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles         3279                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 370702181                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                652815                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          818451212                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.833527                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.163546                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                136785734     16.71%     16.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                223134622     27.26%     43.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 98075130     11.98%     55.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                360455726     44.04%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            818451212                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.285744                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.466445                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                119992571                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             159648210                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 484662538                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              38629741                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               15518152                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             25181026                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 13828                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1248127712                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              39967189                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               15518152                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                177000170                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                78888622                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         210704                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 464955823                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              81877741                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1190635480                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              25549977                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              24948594                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2267380                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               41534187                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1694220                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          1225376851                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5812387634                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1358166964                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          40876517                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                350598621                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               7265                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           7257                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 108139964                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            366113107                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           236095924                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1592417                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5322589                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1168545112                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               12357                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1017136895                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          18518107                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       379832511                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   1032101117                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            203                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     818451212                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.242758                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.084999                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           260801504     31.87%     31.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           227738074     27.83%     59.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           216482418     26.45%     86.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            97282888     11.89%     98.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            16146319      1.97%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                   9      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       818451212                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                64511713     19.12%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  18146      0.01%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead              155540663     46.10%     65.42% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite             116678902     34.58%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             456370981     44.87%     44.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              5195830      0.51%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.06%     45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         2550147      0.25%     46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       11478993      1.13%     47.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            322128329     31.67%     78.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           215587412     21.20%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1017136895                       # Type of FU issued
system.cpu.iq.rate                           1.242264                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   337386313                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.331702                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         3146752380                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1504842501                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    934271178                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads            61877042                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           43565869                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     26152443                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1320712858                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                33810350                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          9960171                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    113872169                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         1090                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        18393                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    107115428                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2065797                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         22350                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               15518152                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                35325435                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 42128                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1168563023                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             366113107                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            236095924                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               6617                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    102                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 45749                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          18393                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       15437385                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3784510                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             19221895                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             974751162                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             303297617                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          42385733                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          5554                       # number of nop insts executed
system.cpu.iew.exec_refs                    497765227                       # number of memory reference insts executed
system.cpu.iew.exec_branches                150613464                       # Number of branches executed
system.cpu.iew.exec_stores                  194467610                       # Number of stores executed
system.cpu.iew.exec_rate                     1.190497                       # Inst execution rate
system.cpu.iew.wb_sent                      963723916                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     960423621                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 536680580                       # num instructions producing a value
system.cpu.iew.wb_consumers                 893282190                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.172998                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.600796                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       357407190                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          15500938                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    767630958                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.027486                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.786865                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    430922921     56.14%     56.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    172477665     22.47%     78.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     73566542      9.58%     88.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     31624091      4.12%     92.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      8540357      1.11%     93.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     14250533      1.86%     95.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      7269334      0.95%     96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      6619169      0.86%     97.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22360346      2.91%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    767630958                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      381221434                       # Number of memory references committed
system.cpu.commit.loads                     252240938                       # Number of loads committed
system.cpu.commit.membars                        5740                       # Number of memory barriers committed
system.cpu.commit.branches                  137364860                       # Number of branches committed
system.cpu.commit.fp_insts                   24239771                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 682251399                       # Number of committed integer instructions.
system.cpu.commit.function_calls             19275340                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        385756794     48.91%     48.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         5173441      0.66%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd       637528      0.08%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp      3187668      0.40%     50.05% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt      2550131      0.32%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc     10203074      1.29%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       252240938     31.98%     83.65% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
system.cpu.commit.bw_lim_events              22360346                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1891399121                       # The number of ROB reads
system.cpu.rob.rob_writes                  2343098694                       # The number of ROB writes
system.cpu.timesIdled                          647342                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          325471                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.278042                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.278042                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.782447                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.782447                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                995806500                       # number of integer regfile reads
system.cpu.int_regfile_writes               567906149                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  31889841                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 22959492                       # number of floating regfile writes
system.cpu.cc_regfile_reads                3794435390                       # number of cc regfile reads
system.cpu.cc_regfile_writes                384898944                       # number of cc regfile writes
system.cpu.misc_regfile_reads               715817585                       # number of misc regfile reads
system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2756184                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.932971                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           414226707                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2756696                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            150.262019                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         257775000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.932971                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999869                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          224                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         839343974                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        839343974                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    286295255                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       286295255                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    127916705                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      127916705                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         3174                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          3174                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     414211960                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        414211960                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    414215134                       # number of overall hits
system.cpu.dcache.overall_hits::total       414215134                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      3031607                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       3031607                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1034772                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1034772                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          647                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          647                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4066379                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4066379                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4067026                       # number of overall misses
system.cpu.dcache.overall_misses::total       4067026                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  35304231919                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  35304231919                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9981686625                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9981686625                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       189500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  45285918544                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  45285918544                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  45285918544                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  45285918544                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    289326862                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    289326862                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         3821                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         3821                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    418278339                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    418278339                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    418282160                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    418282160                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010478                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.010478                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008025                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.008025                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169327                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.169327                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009722                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009722                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009723                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009723                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.385407                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.385407                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9646.266641                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  9646.266641                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.669392                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 11136.669392                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11134.897722                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 11134.897722                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       343566                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets            5188                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    66.223207                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       735673                       # number of writebacks
system.cpu.dcache.writebacks::total            735673                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       996398                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       996398                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       313907                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       313907                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1310305                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1310305                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1310305                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1310305                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035209                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      2035209                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720865                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       720865                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          641                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          641                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2756074                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2756074                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2756715                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2756715                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23117834450                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  23117834450                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5596502782                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5596502782                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5770003                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5770003                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28714337232                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  28714337232                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28720107235                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  28720107235                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005590                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005590                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.167757                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.167757                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006591                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006591                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11358.948614                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11358.948614                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7763.593436                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7763.593436                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  9001.564743                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  9001.564743                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.565406                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.565406                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.235920                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.235920                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           5169973                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.005918                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           365527993                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           5170483                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             70.695135                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle         247768250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.005918                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.998058                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.998058                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          328                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         746574800                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        746574800                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    365528016                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       365528016                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     365528016                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        365528016                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    365528016                       # number of overall hits
system.cpu.icache.overall_hits::total       365528016                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      5174133                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       5174133                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      5174133                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        5174133                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      5174133                       # number of overall misses
system.cpu.icache.overall_misses::total       5174133                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  41647669446                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  41647669446                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  41647669446                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  41647669446                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  41647669446                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  41647669446                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    370702149                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    370702149                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    370702149                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    370702149                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    370702149                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    370702149                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013958                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.013958                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.013958                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.013958                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.013958                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.013958                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8049.207364                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  8049.207364                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  8049.207364                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  8049.207364                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  8049.207364                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  8049.207364                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        75182                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          145                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              3130                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    24.019808                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           29                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3630                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3630                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3630                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3630                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3630                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3630                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5170503                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      5170503                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      5170503                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      5170503                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      5170503                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      5170503                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36431563436                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  36431563436                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36431563436                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  36431563436                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36431563436                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  36431563436                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013948                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013948                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013948                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.013948                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013948                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.013948                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7046.038545                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7046.038545                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7046.038545                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  7046.038545                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7046.038545                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  7046.038545                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued      1347095                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      1354943                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         6866                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage      4789921                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           299164                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16361.556320                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7824806                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           315528                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            24.799086                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      13406100000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   743.987058                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   127.512594                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8771.582471                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6718.474196                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.045409                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007783                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.535375                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.410063                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.998630                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022         6518                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         9846                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           16                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2          171                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1451                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4880                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          169                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          225                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2089                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7268                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.397827                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.600952                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        139642343                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       139642343                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst      5166932                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1926211                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        7093143                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       735673                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       735673                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       717988                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       717988                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst      5166932                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2644199                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7811131                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      5166932                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2644199                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7811131                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3553                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       109639                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       113192                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           18                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           18                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2858                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2858                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3553                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       112497                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        116050                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3553                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       112497                       # number of overall misses
system.cpu.l2cache.overall_misses::total       116050                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    261165964                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   8561744931                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   8822910895                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    205223699                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    205223699                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    261165964                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   8766968630                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   9028134594                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    261165964                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   8766968630                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   9028134594                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      5170485                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      2035850                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7206335                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       735673                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       735673                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           19                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           19                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       720846                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       720846                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      5170485                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2756696                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      7927181                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      5170485                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2756696                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      7927181                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.000687                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.053854                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.015707                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.947368                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.947368                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003965                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.003965                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.000687                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.040809                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.014640                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.000687                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.040809                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.014640                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73505.759640                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78090.323069                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77946.417547                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71806.752624                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71806.752624                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73505.759640                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77930.688196                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77795.214080                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73505.759640                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77930.688196                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77795.214080                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66342                       # number of writebacks
system.cpu.l2cache.writebacks::total            66342                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           14                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data         1287                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total         1301                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1460                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         1460                       # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           14                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         2747                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         2761                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           14                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         2747                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         2761                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3539                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       108352                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       111891                       # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202242                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       202242                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           18                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           18                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1398                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1398                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3539                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       109750                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       113289                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3539                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       109750                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202242                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       315531                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    230067036                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   7609571000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7839638036                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  17078829649                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  17078829649                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       248018                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       248018                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    114010508                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    114010508                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    230067036                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7723581508                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   7953648544                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    230067036                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7723581508                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  17078829649                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  25032478193                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.053222                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015527                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.947368                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.947368                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001939                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001939                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039812                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.014291                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039812                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.039804                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65009.052275                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70230.092661                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.956395                       # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13778.777778                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13778.777778                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65009.052275                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70374.318979                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.715074                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65009.052275                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70374.318979                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.449525                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        7206353                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7206352                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       735673                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       248887                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           19                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           19                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       720846                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       720846                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     10340987                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6249103                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          16590090                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330910976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223511616                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          554422592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      248905                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      8911778                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.027928                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.164766                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            8662891     97.21%     97.21% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4             248887      2.79%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        8911778                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5067118500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    7756291499                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    4138722865                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.membus.trans_dist::ReadReq              314057                       # Transaction distribution
system.membus.trans_dist::ReadResp             314057                       # Transaction distribution
system.membus.trans_dist::Writeback             66342                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               18                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              18                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1398                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1398                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       697288                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 697288                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24435008                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                24435008                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            381815                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  381815    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              381815                       # Request fanout histogram
system.membus.reqLayer0.occupancy           746604866                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1648190996                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)

---------- End Simulation Statistics   ----------