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---------- Begin Simulation Statistics ----------
sim_seconds                                  0.640648                       # Number of seconds simulated
sim_ticks                                640648369500                       # Number of ticks simulated
final_tick                               640648369500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  92518                       # Simulator instruction rate (inst/s)
host_op_rate                                   125998                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               42814979                       # Simulator tick rate (ticks/s)
host_mem_usage                                 256100                       # Number of bytes of host memory used
host_seconds                                 14963.18                       # Real time elapsed on the host
sim_insts                                  1384370590                       # Number of instructions simulated
sim_ops                                    1885325342                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            155648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          30243840                       # Number of bytes read from this memory
system.physmem.bytes_read::total             30399488                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       155648                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          155648                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2432                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             472560                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                474992                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               242954                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             47208174                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                47451128                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          242954                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             242954                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           6603111                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6603111                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           6603111                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              242954                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            47208174                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               54054239                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        474992                       # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs                        66098                       # Total number of write requests accepted by DRAM controller
system.physmem.readBursts                      474992                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts                      66098                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
system.physmem.bytesRead                     30399488                       # Total number of bytes read from memory
system.physmem.bytesWritten                   4230272                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               30399488                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                4230272                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      152                       # Number of DRAM read bursts serviced by write Q
system.physmem.neitherReadNorWrite               4361                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 29873                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 29675                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 29741                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 29701                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 29814                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 29838                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 29642                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 29441                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 29488                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 29488                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                29538                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                29646                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                29708                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                29815                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                29628                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                29804                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  4174                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  4102                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  4138                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  4148                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  4226                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  4225                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  4174                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  4096                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  4096                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  4096                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 4096                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 4097                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 4098                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 4096                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 4096                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 4140                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    640648293500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  474992                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
system.physmem.writePktSize::6                  66098                       # Categorize write packet sizes
system.physmem.rdQLenPdf::0                    407729                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     66641                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       384                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        67                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     2873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     2873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     2873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       173268                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      199.789644                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     132.514067                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     508.333416                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65          59669     34.44%     34.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129        42666     24.62%     59.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193        39942     23.05%     82.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257        25325     14.62%     96.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321          291      0.17%     96.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385          110      0.06%     96.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449          103      0.06%     97.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513           89      0.05%     97.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577           94      0.05%     97.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641           79      0.05%     97.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705           78      0.05%     97.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769           80      0.05%     97.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833           70      0.04%     97.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897           76      0.04%     97.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961           80      0.05%     97.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025           77      0.04%     97.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089           75      0.04%     97.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153           70      0.04%     97.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217           81      0.05%     97.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281           72      0.04%     97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345           78      0.05%     97.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409           72      0.04%     97.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473         3310      1.91%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537            3      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601            3      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665            4      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857            1      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049            2      0.00%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113            1      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177            1      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241            3      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305            1      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369            1      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433            4      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497            1      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561            1      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689            3      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817            1      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009            1      0.00%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073            1      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137            1      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457            1      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649            1      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777            1      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969            1      0.00%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161           78      0.05%     99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225            2      0.00%     99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289            1      0.00%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353            1      0.00%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865            1      0.00%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121            1      0.00%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377            1      0.00%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001            1      0.00%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193          558      0.32%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         173268                       # Bytes accessed per row activation
system.physmem.totQLat                     1888421000                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               14966831000                       # Sum of mem lat for all requests
system.physmem.totBusLat                   2374200000                       # Total cycles spent in databus access
system.physmem.totBankLat                 10704210000                       # Total cycles spent in bank access
system.physmem.avgQLat                        3976.96                       # Average queueing delay per request
system.physmem.avgBankLat                    22542.77                       # Average bank access latency per request
system.physmem.avgBusLat                      5000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  31519.74                       # Average memory access latency
system.physmem.avgRdBW                          47.45                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           6.60                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  47.45                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   6.60                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.42                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.02                       # Average read queue length over time
system.physmem.avgWrQLen                        17.45                       # Average write queue length over time
system.physmem.readRowHits                     318007                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     49644                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   66.97                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.11                       # Row buffer hit rate for writes
system.physmem.avgGap                      1183995.81                       # Average gap between requests
system.membus.throughput                     54054139                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              408917                       # Transaction distribution
system.membus.trans_dist::ReadResp             408916                       # Transaction distribution
system.membus.trans_dist::Writeback             66098                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4361                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4361                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66075                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66075                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1024803                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1024803                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34629696                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            34629696                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               34629696                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1215067500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4480877139                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
system.cpu.branchPred.lookups               451070712                       # Number of BP lookups
system.cpu.branchPred.condPredicted         361199071                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          31575662                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            266989928                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               238695746                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             89.402528                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                53258278                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2806364                       # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1411                       # Number of system calls
system.cpu.numCycles                       1281296740                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          365834433                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2312845521                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   451070712                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          291954024                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     613483563                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               162414515                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              128244265                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  613                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         11411                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          133                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 346004157                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes              12181247                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1238361342                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.567207                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.166964                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                624922537     50.46%     50.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 43984122      3.55%     54.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                100783073      8.14%     62.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 58015364      4.68%     66.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 73986941      5.97%     72.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 44117238      3.56%     76.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 31886448      2.57%     78.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 33644071      2.72%     81.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                227021548     18.33%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1238361342                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.352042                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.805082                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                416001710                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             101876756                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 574960463                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              14748325                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              130774088                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             46845433                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 13115                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3066767432                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 27354                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              130774088                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                450873553                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                37362667                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         459915                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 552824643                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              66066476                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2984722482                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   106                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                4345913                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              52259250                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents               16                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          2968696668                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups           14208671481                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups      12321480350                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          90240197                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1993140090                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                975556578                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              21287                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          18729                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 172024073                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            975055963                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           496398991                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          36275443                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         40590257                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2826416078                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               28152                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2457324643                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          15915709                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       928556403                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   2380098621                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           6768                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1238361342                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.984336                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.868331                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           394006079     31.82%     31.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           183256590     14.80%     46.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           205523874     16.60%     63.21% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           174394872     14.08%     77.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           137878376     11.13%     88.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            90899666      7.34%     95.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            36275985      2.93%     98.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            12839255      1.04%     99.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             3286645      0.27%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1238361342                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  691696      0.78%      0.78% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  24382      0.03%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               55024342     62.24%     63.05% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              32666949     36.95%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1118619814     45.52%     45.52% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult             11223087      0.46%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     46.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     46.03% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         6876474      0.28%     46.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         5501669      0.22%     46.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     46.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       23389012      0.95%     47.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.49% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.49% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            843037947     34.31%     81.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           447301347     18.20%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2457324643                       # Type of FU issued
system.cpu.iq.rate                           1.917842                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    88407369                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.035977                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6133604202                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3666175191                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2269813505                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           123729504                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           88892403                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     56421926                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2481804628                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                63927384                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         85672552                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    343668782                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        27729                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation      1429255                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    219403694                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           304                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              130774088                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                15649984                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1558990                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2826456693                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            641968                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             975055963                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            496398991                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              18166                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1553675                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  2519                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents        1429255                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       33789507                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      2118647                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             35908154                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2378923796                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             796860173                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          78400847                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         12463                       # number of nop insts executed
system.cpu.iew.exec_refs                   1223764024                       # number of memory reference insts executed
system.cpu.iew.exec_branches                324680497                       # Number of branches executed
system.cpu.iew.exec_stores                  426903851                       # Number of stores executed
system.cpu.iew.exec_rate                     1.856653                       # Inst execution rate
system.cpu.iew.wb_sent                     2351973532                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2326235431                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1354756756                       # num instructions producing a value
system.cpu.iew.wb_consumers                2530303455                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.815532                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.535413                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       941120455                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           21384                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          31562826                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1107587254                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.702201                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.378361                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    463154673     41.82%     41.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    291887882     26.35%     68.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     96478924      8.71%     76.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     70059146      6.33%     83.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     46846853      4.23%     87.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     22330225      2.02%     89.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     15798039      1.43%     90.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     11765677      1.06%     91.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     89265835      8.06%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1107587254                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1384381606                       # Number of instructions committed
system.cpu.commit.committedOps             1885336358                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      908382478                       # Number of memory references committed
system.cpu.commit.loads                     631387181                       # Number of loads committed
system.cpu.commit.membars                        9986                       # Number of memory barriers committed
system.cpu.commit.branches                  298259106                       # Number of branches committed
system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1653698867                       # Number of committed integer instructions.
system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              89265835                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   3844759887                       # The number of ROB reads
system.cpu.rob.rob_writes                  5783698867                       # The number of ROB writes
system.cpu.timesIdled                          353367                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        42935398                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1384370590                       # Number of Instructions Simulated
system.cpu.committedOps                    1885325342                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1384370590                       # Number of Instructions Simulated
system.cpu.cpi                               0.925545                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.925545                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.080445                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.080445                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads              11851555490                       # number of integer regfile reads
system.cpu.int_regfile_writes              2239006966                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  68795802                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 49533000                       # number of floating regfile writes
system.cpu.misc_regfile_reads              1371543913                       # number of misc regfile reads
system.cpu.misc_regfile_writes               13772902                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               165989839                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        1492758                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1492757                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback        96304                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         4364                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         4364                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        72519                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        72519                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52387                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3178835                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3231222                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1536768                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104525120                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      106061888                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         106061888                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       279232                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      929276999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      43029998                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2407943085                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
system.cpu.icache.tags.replacements             22329                       # number of replacements
system.cpu.icache.tags.tagsinuse          1638.931929                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           345969528                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             24011                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          14408.792970                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1638.931929                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.800260                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.800260                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    345973619                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       345973619                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     345973619                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        345973619                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    345973619                       # number of overall hits
system.cpu.icache.overall_hits::total       345973619                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        30537                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         30537                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        30537                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          30537                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        30537                       # number of overall misses
system.cpu.icache.overall_misses::total         30537                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    527751245                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    527751245                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    527751245                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    527751245                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    527751245                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    527751245                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    346004156                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    346004156                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    346004156                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    346004156                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    346004156                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    346004156                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000088                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000088                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000088                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000088                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000088                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000088                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17282.354030                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 17282.354030                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17282.354030                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 17282.354030                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17282.354030                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 17282.354030                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1734                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                32                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    54.187500                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2162                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2162                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2162                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2162                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2162                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2162                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        28375                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        28375                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        28375                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        28375                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        28375                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        28375                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    422292499                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    422292499                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    422292499                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    422292499                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    422292499                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    422292499                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000082                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000082                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000082                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000082                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000082                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000082                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14882.555031                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14882.555031                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14882.555031                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14882.555031                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14882.555031                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14882.555031                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           442208                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32680.533022                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1109569                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           474957                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.336146                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  1291.826262                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    50.114345                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31338.592416                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.039423                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001529                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.956378                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.997331                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        21578                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1057872                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1079450                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks        96304                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total        96304                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         6444                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         6444                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        21578                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1064316                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1085894                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        21578                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1064316                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1085894                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2434                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       406511                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       408945                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         4361                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         4361                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66075                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66075                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2434                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       472586                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        475020                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2434                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       472586                       # number of overall misses
system.cpu.l2cache.overall_misses::total       475020                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    173732500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  30711118250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  30884850750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4593677250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   4593677250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    173732500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  35304795500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  35478528000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    173732500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  35304795500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  35478528000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        24012                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1464383                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1488395                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks        96304                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total        96304                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4364                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         4364                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        72519                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        72519                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        24012                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1536902                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1560914                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        24012                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1536902                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1560914                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.101366                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.277599                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.274756                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999313                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999313                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911141                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.911141                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.101366                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.307493                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.304322                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.101366                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.307493                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.304322                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71377.362366                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75548.062045                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75523.238455                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69522.167991                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69522.167991                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71377.362366                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74705.546715                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74688.493116                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71377.362366                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74705.546715                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74688.493116                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           26                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           28                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           26                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           28                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           26                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           28                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2432                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406485                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       408917                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4361                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         4361                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66075                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66075                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2432                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       472560                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       474992                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2432                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       472560                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       474992                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    142964000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  25574268250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  25717232250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     43614361                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     43614361                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3760538250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3760538250                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    142964000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  29334806500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  29477770500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    142964000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  29334806500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  29477770500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.101283                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.277581                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.274737                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999313                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999313                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911141                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911141                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.101283                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.307476                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.304304                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.101283                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.307476                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.304304                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58784.539474                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62915.650639                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62891.081197                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56913.178207                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56913.178207                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58784.539474                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62076.363848                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62059.509423                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58784.539474                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62076.363848                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62059.509423                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1532805                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4094.435174                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           972917364                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1536901                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            633.038409                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         392115250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4094.435174                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999618                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999618                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    696790485                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       696790485                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    276093216                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      276093216                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10000                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10000                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         9985                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     972883701                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        972883701                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    972883701                       # number of overall hits
system.cpu.dcache.overall_hits::total       972883701                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1953888                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1953888                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       842462                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       842462                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2796350                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2796350                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2796350                       # number of overall misses
system.cpu.dcache.overall_misses::total       2796350                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  79173694807                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  79173694807                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  56852278531                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  56852278531                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       204750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       204750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 136025973338                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 136025973338                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 136025973338                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 136025973338                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    698744373                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    698744373                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10003                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10003                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         9985                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    975680051                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    975680051                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    975680051                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    975680051                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002796                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002796                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003042                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.003042                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000300                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000300                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002866                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002866                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002866                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002866                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40521.101930                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40521.101930                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67483.493061                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 67483.493061                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        68250                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        68250                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48644.115843                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 48644.115843                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 48644.115843                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 48644.115843                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         2745                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          853                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                62                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              89                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    44.274194                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     9.584270                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        96304                       # number of writebacks
system.cpu.dcache.writebacks::total             96304                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       489504                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       489504                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       765580                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       765580                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1255084                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1255084                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1255084                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1255084                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464384                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1464384                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        76882                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        76882                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1541266                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1541266                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1541266                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1541266                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  42754567776                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  42754567776                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4832230139                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4832230139                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47586797915                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  47586797915                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47586797915                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  47586797915                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002096                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002096                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000278                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000278                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001580                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001580                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001580                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001580                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------