path: root/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.407884                       # Number of seconds simulated
sim_ticks                                407883784500                       # Number of ticks simulated
final_tick                               407883784500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 135225                       # Simulator instruction rate (inst/s)
host_op_rate                                   166480                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               86093843                       # Simulator tick rate (ticks/s)
host_mem_usage                                2533572                       # Number of bytes of host memory used
host_seconds                                  4737.67                       # Real time elapsed on the host
sim_insts                                   640649298                       # Number of instructions simulated
sim_ops                                     788724957                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst             63360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           6867584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     13490752                       # Number of bytes read from this memory
system.physmem.bytes_read::total             20421696                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        63360                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           63360                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4243968                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4243968                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                990                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             107306                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       210793                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                319089                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66312                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66312                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               155338                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             16837110                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     33074990                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                50067438                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          155338                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             155338                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          10404846                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               10404846                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          10404846                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              155338                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            16837110                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     33074990                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               60472284                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        319089                       # Number of read requests accepted
system.physmem.writeReqs                        66312                       # Number of write requests accepted
system.physmem.readBursts                      319089                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66312                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 20403200                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     18496                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4238016                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  20421696                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4243968                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      289                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      64                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             19                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               20089                       # Per bank write bursts
system.physmem.perBankRdBursts::1               19545                       # Per bank write bursts
system.physmem.perBankRdBursts::2               20086                       # Per bank write bursts
system.physmem.perBankRdBursts::3               20646                       # Per bank write bursts
system.physmem.perBankRdBursts::4               19933                       # Per bank write bursts
system.physmem.perBankRdBursts::5               20704                       # Per bank write bursts
system.physmem.perBankRdBursts::6               19571                       # Per bank write bursts
system.physmem.perBankRdBursts::7               19471                       # Per bank write bursts
system.physmem.perBankRdBursts::8               19556                       # Per bank write bursts
system.physmem.perBankRdBursts::9               19505                       # Per bank write bursts
system.physmem.perBankRdBursts::10              19502                       # Per bank write bursts
system.physmem.perBankRdBursts::11              20173                       # Per bank write bursts
system.physmem.perBankRdBursts::12              19634                       # Per bank write bursts
system.physmem.perBankRdBursts::13              20280                       # Per bank write bursts
system.physmem.perBankRdBursts::14              19577                       # Per bank write bursts
system.physmem.perBankRdBursts::15              20528                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4247                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4105                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4143                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4151                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4245                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4232                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4095                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4153                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    407883730500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  319089                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66312                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    124916                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    114317                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     15700                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      7222                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6886                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      7870                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      9271                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      8234                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      7181                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4414                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     4114                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2941                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     2294                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1703                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                     1093                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      644                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      595                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      627                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                      958                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1673                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     2929                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3407                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4840                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5620                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5402                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4546                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4208                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4070                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4033                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      188                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      155                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      115                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      101                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      109                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       86                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       73                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       10                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       138324                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      178.138053                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     128.082938                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     199.804046                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          55124     39.85%     39.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        58239     42.10%     81.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        14671     10.61%     92.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          966      0.70%     93.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1420      1.03%     94.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1368      0.99%     95.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1462      1.06%     96.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1224      0.88%     97.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3850      2.78%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         138324                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4017                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        67.829475                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       35.454654                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      482.917109                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            3981     99.10%     99.10% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023           15      0.37%     99.48% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535            5      0.12%     99.60% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1536-2047            4      0.10%     99.70% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2559            3      0.07%     99.78% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-3071            2      0.05%     99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-3583            1      0.02%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119            1      0.02%     99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5632-6143            1      0.02%     99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-12799            1      0.02%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            2      0.05%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::15872-16383            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4017                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4017                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.484690                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.435555                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.421529                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3367     83.82%     83.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  9      0.22%     84.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                437     10.88%     94.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 79      1.97%     96.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 37      0.92%     97.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 18      0.45%     98.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 15      0.37%     98.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 22      0.55%     99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 13      0.32%     99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  3      0.07%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  6      0.15%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  2      0.05%     99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  3      0.07%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  2      0.05%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  1      0.02%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  2      0.05%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4017                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9958454882                       # Total ticks spent queuing
system.physmem.totMemAccLat               15935954882                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1594000000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       31237.31                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  49987.31                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          50.02                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          10.39                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       50.07                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       10.40                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.47                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.39                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.08                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.59                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.53                       # Average write queue length when enqueuing
system.physmem.readRowHits                     219908                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     26785                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   68.98                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  40.43                       # Row buffer hit rate for writes
system.physmem.avgGap                      1058335.94                       # Average gap between requests
system.physmem.pageHitRate                      64.07                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     155274651966                       # Time in different power states
system.physmem.memoryStateTime::REF       13620100000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      238988228034                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.physmem.actEnergy::0                 524928600                       # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1                 520778160                       # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0                 286419375                       # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1                 284154750                       # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0               1248351000                       # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1               1238000400                       # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0               216380160                       # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1               212718960                       # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0           26640915600                       # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1           26640915600                       # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0           97043660235                       # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1           97028348895                       # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0          159603762000                       # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1          159617193000                       # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0            285564416970                       # Total energy per rank (pJ)
system.physmem.totalEnergy::1            285542109765                       # Total energy per rank (pJ)
system.physmem.averagePower::0             700.113612                       # Core power per rank (mW)
system.physmem.averagePower::1             700.058922                       # Core power per rank (mW)
system.membus.trans_dist::ReadReq              317731                       # Transaction distribution
system.membus.trans_dist::ReadResp             317731                       # Transaction distribution
system.membus.trans_dist::Writeback             66312                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               19                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              19                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1358                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1358                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       704528                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 704528                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24665664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                24665664                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            385420                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  385420    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              385420                       # Request fanout histogram
system.membus.reqLayer0.occupancy           968060850                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         2930140600                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               233961455                       # Number of BP lookups
system.cpu.branchPred.condPredicted         161822903                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          15515021                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            121571694                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               108258179                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             89.048836                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                25034450                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1300530                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  673                       # Number of system calls
system.cpu.numCycles                        815767570                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           84062545                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1200075862                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   233961455                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          133292629                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     716015819                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                31064711                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  216                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles         1031                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 370072724                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                652087                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          815611997                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.839157                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.161407                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                134572174     16.50%     16.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                222502254     27.28%     43.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 98076609     12.02%     55.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                360460960     44.20%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            815611997                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.286799                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.471100                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                119967047                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             156830594                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 484662032                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              38633655                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               15518669                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             25180757                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 13832                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1248142745                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              39968083                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               15518669                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                176978211                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                77349013                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         209115                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 464956606                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              80600383                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1190653187                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              25546667                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              24946830                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2267986                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               40254462                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1692453                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          1225396135                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5812466885                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1358185264                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          40876472                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                350617905                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               7272                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           7264                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 108149104                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            366119032                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           236098756                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1753479                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5371728                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1168565166                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               12360                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1017100859                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          18396242                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       379746204                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   1032205063                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            206                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     815611997                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.247040                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.084974                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           257903097     31.62%     31.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           228438073     28.01%     59.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           215325690     26.40%     86.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            97769150     11.99%     98.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            16175979      1.98%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                   8      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       815611997                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                64512923     19.13%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  18147      0.01%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead              155504488     46.10%     65.42% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite             116641749     34.58%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             456383765     44.87%     44.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              5195693      0.51%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.06%     45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         2550151      0.25%     46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       11478998      1.13%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            322094029     31.67%     78.81% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           215573019     21.19%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1017100859                       # Type of FU issued
system.cpu.iq.rate                           1.246802                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   337314196                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.331643                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         3143647062                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1504776491                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    934274751                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads            61877091                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           43565761                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     26152451                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1320604680                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                33810375                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          9960281                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    113878094                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         1252                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        18526                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    107118260                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2065804                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         23979                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               15518669                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                35328826                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                675397                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1168583078                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             366119032                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            236098756                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               6620                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    121                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                678981                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          18526                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       15437712                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3784771                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             19222483                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             974757504                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             303300667                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          42343355                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          5552                       # number of nop insts executed
system.cpu.iew.exec_refs                    497757295                       # number of memory reference insts executed
system.cpu.iew.exec_branches                150614518                       # Number of branches executed
system.cpu.iew.exec_stores                  194456628                       # Number of stores executed
system.cpu.iew.exec_rate                     1.194896                       # Inst execution rate
system.cpu.iew.wb_sent                      963726633                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     960427202                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 536683301                       # num instructions producing a value
system.cpu.iew.wb_consumers                 893293358                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.177329                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.600792                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       357423726                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          15501335                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    764789514                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.031303                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.790973                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    428726988     56.06%     56.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    171833427     22.47%     78.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     73566428      9.62%     88.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     31619643      4.13%     92.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      7902471      1.03%     93.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     14889027      1.95%     95.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      7271717      0.95%     96.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      6618968      0.87%     97.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22360845      2.92%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    764789514                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            640654410                       # Number of instructions committed
system.cpu.commit.committedOps              788730069                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      381221434                       # Number of memory references committed
system.cpu.commit.loads                     252240938                       # Number of loads committed
system.cpu.commit.membars                        5740                       # Number of memory barriers committed
system.cpu.commit.branches                  137364859                       # Number of branches committed
system.cpu.commit.fp_insts                   24239771                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 682251399                       # Number of committed integer instructions.
system.cpu.commit.function_calls             19275340                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        385756793     48.91%     48.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         5173441      0.66%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd       637528      0.08%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp      3187668      0.40%     50.05% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt      2550131      0.32%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc     10203074      1.29%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       252240938     31.98%     83.65% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         788730069                       # Class of committed instruction
system.cpu.commit.bw_lim_events              22360845                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   1888573713                       # The number of ROB reads
system.cpu.rob.rob_writes                  2343133826                       # The number of ROB writes
system.cpu.timesIdled                          646395                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          155573                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   640649298                       # Number of Instructions Simulated
system.cpu.committedOps                     788724957                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.273345                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.273345                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.785333                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.785333                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                995802642                       # number of integer regfile reads
system.cpu.int_regfile_writes               567917186                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  31889847                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 22959506                       # number of floating regfile writes
system.cpu.cc_regfile_reads                3794452598                       # number of cc regfile reads
system.cpu.cc_regfile_writes                384905504                       # number of cc regfile writes
system.cpu.misc_regfile_reads               715806131                       # number of misc regfile reads
system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
system.cpu.toL2Bus.trans_dist::ReadReq        7205652                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7205652                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       735005                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq      9840757                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           20                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           20                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       720847                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       720847                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     10339627                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6248397                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          16588024                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330867456                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223467584                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          554335040                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     9840776                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     18503299                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        5.531838                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.498985                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5            8662542     46.82%     46.82% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6            9840757     53.18%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            5                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            6                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       18503299                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5066671498                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    7754858551                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    4142472532                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements           5169293                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.870067                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           364901080                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           5169803                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             70.583169                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle         199337500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.870067                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997793                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997793                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          118                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          325                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         745315243                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        745315243                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    364901109                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       364901109                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     364901109                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        364901109                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    364901109                       # number of overall hits
system.cpu.icache.overall_hits::total       364901109                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      5171601                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       5171601                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      5171601                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        5171601                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      5171601                       # number of overall misses
system.cpu.icache.overall_misses::total       5171601                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  41478755019                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  41478755019                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  41478755019                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  41478755019                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  41478755019                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  41478755019                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    370072710                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    370072710                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    370072710                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    370072710                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    370072710                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    370072710                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013975                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.013975                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.013975                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.013975                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.013975                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.013975                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8020.486310                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  8020.486310                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  8020.486310                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  8020.486310                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  8020.486310                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  8020.486310                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        17792                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              1782                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs     9.984287                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1778                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         1778                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         1778                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         1778                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         1778                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         1778                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5169823                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      5169823                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      5169823                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      5169823                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      5169823                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      5169823                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  33703861415                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  33703861415                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  33703861415                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  33703861415                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  33703861415                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  33703861415                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013970                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013970                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013970                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.013970                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013970                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.013970                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  6519.345327                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  6519.345327                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  6519.345327                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  6519.345327                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  6519.345327                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  6519.345327                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified     42714534                       # number of hwpf identified
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr       332916                       # number of hwpf that were already in mshr
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache     32636070                       # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher        18709                       # number of hwpf that were already in the prefetch queue
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit         3827                       # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued      9723012                       # number of hwpf issued
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page      4810754                       # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.tags.replacements           302773                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16364.911497                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7827990                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           319143                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            24.528158                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      12938833000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   727.090986                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    49.045333                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8487.644412                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  7101.130766                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.044378                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002993                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.518045                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.433419                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.998835                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022         7180                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         9190                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0          155                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1          246                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2          170                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1499                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4         5110                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          233                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2000                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         6801                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.438232                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.560913                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        139624071                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       139624071                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst      5168280                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1928699                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        7096979                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       735005                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       735005                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       718110                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       718110                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst      5168280                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2646809                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7815089                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      5168280                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2646809                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7815089                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         1524                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       107130                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       108654                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           19                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           19                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2737                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2737                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         1524                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       109867                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        111391                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         1524                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       109867                       # number of overall misses
system.cpu.l2cache.overall_misses::total       111391                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    107432161                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   7354763933                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   7462196094                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    174400348                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    174400348                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    107432161                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   7529164281                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   7636596442                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    107432161                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   7529164281                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   7636596442                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      5169804                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      2035829                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7205633                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       735005                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       735005                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           20                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           20                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       720847                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       720847                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      5169804                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2756676                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      7926480                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      5169804                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2756676                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      7926480                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.000295                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.052622                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.015079                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.950000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.950000                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003797                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.003797                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.000295                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.039855                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.014053                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.000295                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.039855                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.014053                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70493.543963                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68652.701699                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68678.521674                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63719.527950                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63719.527950                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70493.543963                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68529.806775                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 68556.673717                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70493.543963                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68529.806775                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 68556.673717                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs       126545                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs             2364                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs    53.530034                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66312                       # number of writebacks
system.cpu.l2cache.writebacks::total            66312                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst          534                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data         1182                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total         1716                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1379                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         1379                       # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst          534                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         2561                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         3095                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst          534                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         2561                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         3095                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          990                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       105948                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       106938                       # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      9723012                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total      9723012                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           19                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           19                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1358                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1358                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          990                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       107306                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       108296                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          990                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       107306                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      9723012                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      9831308                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     71873499                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   6404181248                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   6476054747                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  19431970184                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  19431970184                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       143518                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       143518                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     92793756                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     92793756                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     71873499                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6496975004                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   6568848503                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     71873499                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6496975004                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  19431970184                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  26000818687                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.000191                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.052042                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.014841                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.950000                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.950000                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001884                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001884                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000191                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.038926                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.013663                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000191                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.038926                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     1.240312                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72599.493939                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60446.457205                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60558.966382                       # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  1998.554582                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  1998.554582                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data  7553.578947                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total  7553.578947                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68331.189985                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68331.189985                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72599.493939                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60546.241627                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.427781                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72599.493939                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60546.241627                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  1998.554582                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total  2644.695771                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           2756164                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.948880                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           414248795                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2756676                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            150.271122                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         207459500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.948880                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999900                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999900                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          220                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          187                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         839347154                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        839347154                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    286297439                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       286297439                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    127936631                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      127936631                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         3157                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          3157                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     414234070                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        414234070                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    414237227                       # number of overall hits
system.cpu.dcache.overall_hits::total       414237227                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      3031039                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       3031039                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1014846                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1014846                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          648                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          648                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4045885                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4045885                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4046533                       # number of overall misses
system.cpu.dcache.overall_misses::total       4046533                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  33719933619                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  33719933619                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9704111685                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9704111685                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       169500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       169500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  43424045304                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  43424045304                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  43424045304                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  43424045304                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    289328478                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    289328478                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         3805                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         3805                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    418279955                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    418279955                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    418283760                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    418283760                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010476                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.010476                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.007870                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.007870                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.170302                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.170302                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009673                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009673                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009674                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009674                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11124.876196                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11124.876196                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9562.151977                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  9562.151977                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        56500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        56500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10732.891643                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 10732.891643                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10731.172909                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 10731.172909                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           23                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       339239                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets            5513                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    11.500000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    61.534373                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       735005                       # number of writebacks
system.cpu.dcache.writebacks::total            735005                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       995853                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       995853                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       293979                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       293979                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1289832                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1289832                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1289832                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1289832                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035186                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      2035186                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720867                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       720867                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          643                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          643                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2756053                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2756053                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2756696                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2756696                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  20990186992                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  20990186992                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5237168826                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5237168826                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5228000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5228000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26227355818                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  26227355818                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26232583818                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  26232583818                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005590                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005590                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168988                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168988                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006590                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006590                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10313.645530                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10313.645530                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7265.097204                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7265.097204                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8130.637636                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8130.637636                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  9516.274113                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total  9516.274113                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  9515.950913                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total  9515.950913                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------