path: root/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.628792                       # Number of seconds simulated
sim_ticks                                628791732500                       # Number of ticks simulated
final_tick                               628791732500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  86286                       # Simulator instruction rate (inst/s)
host_op_rate                                   117510                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               39191918                       # Simulator tick rate (ticks/s)
host_mem_usage                                 321468                       # Number of bytes of host memory used
host_seconds                                 16043.91                       # Real time elapsed on the host
sim_insts                                  1384370590                       # Number of instructions simulated
sim_ops                                    1885325342                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            154944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          30242560                       # Number of bytes read from this memory
system.physmem.bytes_read::total             30397504                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       154944                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          154944                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2421                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             472540                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                474961                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               246415                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             48096307                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                48342722                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          246415                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             246415                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           6727620                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6727620                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           6727620                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              246415                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            48096307                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               55070342                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        474962                       # Number of read requests accepted
system.physmem.writeReqs                        66098                       # Number of write requests accepted
system.physmem.readBursts                      474962                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 30374848                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     22720                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4229184                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  30397568                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      355                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4292                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               29853                       # Per bank write bursts
system.physmem.perBankRdBursts::1               29663                       # Per bank write bursts
system.physmem.perBankRdBursts::2               29734                       # Per bank write bursts
system.physmem.perBankRdBursts::3               29691                       # Per bank write bursts
system.physmem.perBankRdBursts::4               29781                       # Per bank write bursts
system.physmem.perBankRdBursts::5               29812                       # Per bank write bursts
system.physmem.perBankRdBursts::6               29626                       # Per bank write bursts
system.physmem.perBankRdBursts::7               29426                       # Per bank write bursts
system.physmem.perBankRdBursts::8               29463                       # Per bank write bursts
system.physmem.perBankRdBursts::9               29476                       # Per bank write bursts
system.physmem.perBankRdBursts::10              29540                       # Per bank write bursts
system.physmem.perBankRdBursts::11              29638                       # Per bank write bursts
system.physmem.perBankRdBursts::12              29686                       # Per bank write bursts
system.physmem.perBankRdBursts::13              29802                       # Per bank write bursts
system.physmem.perBankRdBursts::14              29621                       # Per bank write bursts
system.physmem.perBankRdBursts::15              29795                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4173                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4102                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4137                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4171                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4093                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4094                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4139                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    628791712500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  474962                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    407661                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     66594                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       276                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        58                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      981                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      983                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3990                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4016                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4011                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4008                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4007                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       194074                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      178.290755                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     128.832062                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     207.398992                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          73771     38.01%     38.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        88634     45.67%     83.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        20233     10.43%     94.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511          463      0.24%     94.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          411      0.21%     94.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          515      0.27%     94.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          585      0.30%     95.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          564      0.29%     95.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8898      4.58%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         194074                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4007                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        48.655603                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       36.114528                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      505.912792                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           4004     99.93%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4007                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4007                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.491390                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.469672                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.863565                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3025     75.49%     75.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  1      0.02%     75.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                975     24.33%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                  6      0.15%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4007                       # Writes before turning the bus around for reads
system.physmem.totQLat                     5771153000                       # Total ticks spent queuing
system.physmem.totMemAccLat               14670034250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2373035000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       12159.86                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30909.86                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          48.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           6.73                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       48.34                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        6.73                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        18.42                       # Average write queue length when enqueuing
system.physmem.readRowHits                     296657                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     49944                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   62.51                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.56                       # Row buffer hit rate for writes
system.physmem.avgGap                      1162147.84                       # Average gap between requests
system.physmem.pageHitRate                      64.10                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE     162139876750                       # Time in different power states
system.physmem.memoryStateTime::REF       20996560000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT      445650242000                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                     55070241                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              408884                       # Transaction distribution
system.membus.trans_dist::ReadResp             408882                       # Transaction distribution
system.membus.trans_dist::Writeback             66098                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4292                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4292                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66078                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66078                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1024604                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1024604                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34627712                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            34627712                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               34627712                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1214449500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4441072458                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               439434227                       # Number of BP lookups
system.cpu.branchPred.condPredicted         352242826                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          30627071                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            250632586                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               230940186                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             92.142921                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                52229993                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2805540                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1411                       # Number of system calls
system.cpu.numCycles                       1257583466                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          355252330                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2281557009                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   439434227                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          283170179                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     601713503                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               156847289                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              133155767                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  595                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         11076                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          125                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 335955320                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes              11758504                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1216301526                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.576674                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.174492                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                614632846     50.53%     50.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 42470987      3.49%     54.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 96126752      7.90%     61.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 57281313      4.71%     66.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 72527941      5.96%     72.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 45003441      3.70%     76.30% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 31089370      2.56%     78.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 31572340      2.60%     81.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                225596536     18.55%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1216301526                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.349427                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.814239                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                405937331                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             105620938                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 561845304                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              16741500                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              126156453                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             44653834                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 11972                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3026383079                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 27573                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              126156453                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                441649817                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                37679339                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         449718                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 540872152                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              69494047                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2944559238                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    81                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                4802711                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              54195204                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              788                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          2928884357                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups           14250328437                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups      12163279231                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          83987601                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1993140090                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                935744267                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              20476                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          17997                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 177752072                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            970380112                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           488270478                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          36212412                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         40741930                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2792865970                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               27850                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2433397099                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          13404605                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       895018158                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   2348989049                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           6466                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1216301526                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.000653                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.872636                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           380324245     31.27%     31.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           183454055     15.08%     46.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           204117167     16.78%     63.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           169768830     13.96%     77.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           132683622     10.91%     88.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            92575300      7.61%     95.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            37909888      3.12%     98.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            12415448      1.02%     99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             3052971      0.25%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1216301526                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  714605      0.81%      0.81% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  24383      0.03%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               55145870     62.89%     63.73% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              31799244     36.27%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1104322039     45.38%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult             11223967      0.46%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         6876477      0.28%     46.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         5502004      0.23%     46.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       23392771      0.96%     47.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            838298218     34.45%     81.82% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           442406331     18.18%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2433397099                       # Type of FU issued
system.cpu.iq.rate                           1.934979                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    87684102                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.036034                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6061689588                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3605336566                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2248845458                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           122494843                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           82642602                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     56425705                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2457771318                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                63309883                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         84349734                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    338992931                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        10163                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation      1428185                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    211275181                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           448                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              126156453                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                15953141                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1561672                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2792906296                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1415032                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             970380112                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            488270478                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              17864                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1555530                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  2527                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents        1428185                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       32514856                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      1483129                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             33997985                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2358061254                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             792590559                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          75335845                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         12476                       # number of nop insts executed
system.cpu.iew.exec_refs                   1216220468                       # number of memory reference insts executed
system.cpu.iew.exec_branches                319843836                       # Number of branches executed
system.cpu.iew.exec_stores                  423629909                       # Number of stores executed
system.cpu.iew.exec_rate                     1.875073                       # Inst execution rate
system.cpu.iew.wb_sent                     2330961284                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2305271163                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1347649196                       # num instructions producing a value
system.cpu.iew.wb_consumers                2523801543                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.833096                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.533976                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       907570051                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           21384                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          30615394                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1090145073                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.729436                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.397108                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    449857024     41.27%     41.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    288588820     26.47%     67.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     95106380      8.72%     76.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     70218402      6.44%     82.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     46473981      4.26%     87.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     22183134      2.03%     89.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     15845043      1.45%     90.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     10980592      1.01%     91.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     90891697      8.34%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1090145073                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1384381606                       # Number of instructions committed
system.cpu.commit.committedOps             1885336358                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      908382478                       # Number of memory references committed
system.cpu.commit.loads                     631387181                       # Number of loads committed
system.cpu.commit.membars                        9986                       # Number of memory barriers committed
system.cpu.commit.branches                  298259106                       # Number of branches committed
system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1653698867                       # Number of committed integer instructions.
system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        930022484     49.33%     49.33% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult        11168279      0.59%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     49.92% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd      1375288      0.07%     49.99% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     49.99% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp      6876469      0.36%     50.36% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt      5501172      0.29%     50.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     50.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc     22010188      1.17%     51.82% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     51.82% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.82% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.82% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       631387181     33.49%     85.31% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      276995297     14.69%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total        1885336358                       # Class of committed instruction
system.cpu.commit.bw_lim_events              90891697                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   3792141440                       # The number of ROB reads
system.cpu.rob.rob_writes                  5711980108                       # The number of ROB writes
system.cpu.timesIdled                          352856                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        41281940                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1384370590                       # Number of Instructions Simulated
system.cpu.committedOps                    1885325342                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.908415                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.908415                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.100818                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.100818                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads              11756762903                       # number of integer regfile reads
system.cpu.int_regfile_writes              2218718479                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  68795802                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 49537143                       # number of floating regfile writes
system.cpu.misc_regfile_reads              1677857394                       # number of misc regfile reads
system.cpu.misc_regfile_writes               13772902                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               169149196                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        1493034                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1493032                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback        96318                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         4295                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         4295                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        72519                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        72519                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        52723                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3178995                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3231718                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1549696                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104535104                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      106084800                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         106084800                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       274816                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      929401499                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      43182746                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2371256268                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
system.cpu.icache.tags.replacements             22529                       # number of replacements
system.cpu.icache.tags.tagsinuse          1644.627190                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           335917634                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             24213                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          13873.441292                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1644.627190                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.803041                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.803041                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1684                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1552                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.822266                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         671939144                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        671939144                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    335924107                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       335924107                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     335924107                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        335924107                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    335924107                       # number of overall hits
system.cpu.icache.overall_hits::total       335924107                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        31211                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         31211                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        31211                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          31211                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        31211                       # number of overall misses
system.cpu.icache.overall_misses::total         31211                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    530208992                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    530208992                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    530208992                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    530208992                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    530208992                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    530208992                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    335955318                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    335955318                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    335955318                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    335955318                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    335955318                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    335955318                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000093                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000093                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000093                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000093                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000093                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000093                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16987.888629                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16987.888629                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16987.888629                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16987.888629                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16987.888629                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16987.888629                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1881                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                32                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    58.781250                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2702                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2702                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2702                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2702                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2702                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2702                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        28509                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        28509                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        28509                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        28509                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        28509                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        28509                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    424344751                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    424344751                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    424344751                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    424344751                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    424344751                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    424344751                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000085                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000085                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000085                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000085                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000085                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000085                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14884.589112                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14884.589112                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14884.589112                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14884.589112                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14884.589112                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14884.589112                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           442179                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32677.883650                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1109649                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           474925                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.336472                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  1317.007846                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    51.079905                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31309.795899                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.040192                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001559                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.955499                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.997250                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32746                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          149                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          509                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5033                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26955                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999329                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         13842423                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        13842423                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        21791                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1058039                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1079830                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks        96318                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total        96318                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         6441                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         6441                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        21791                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1064480                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1086271                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        21791                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1064480                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1086271                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2424                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       406486                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       408910                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         4292                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         4292                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66078                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66078                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2424                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       472564                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        474988                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2424                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       472564                       # number of overall misses
system.cpu.l2cache.overall_misses::total       474988                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    173590500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  30155031750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  30328622250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4756999500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   4756999500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    173590500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  34912031250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  35085621750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    173590500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  34912031250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  35085621750                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        24215                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1464525                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1488740                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks        96318                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total        96318                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4295                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         4295                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        72519                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        72519                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        24215                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1537044                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1561259                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        24215                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1537044                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1561259                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.100103                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.277555                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.274669                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999302                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999302                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911182                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.911182                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.100103                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.307450                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.304234                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.100103                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.307450                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.304234                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71613.242574                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74184.674872                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74169.431538                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71990.670117                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71990.670117                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71613.242574                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73877.890085                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73866.332939                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71613.242574                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73877.890085                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73866.332939                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           24                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           26                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           26                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           24                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           26                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2422                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406462                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       408884                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4292                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         4292                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66078                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66078                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2422                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       472540                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       474962                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2422                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       472540                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       474962                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    143052750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  25094264500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  25237317250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     42924292                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     42924292                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3924413500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3924413500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    143052750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  29018678000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  29161730750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    143052750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  29018678000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  29161730750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.100021                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.277538                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.274651                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999302                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999302                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911182                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911182                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.100021                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.307434                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.304217                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.100021                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.307434                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.304217                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59063.893476                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61738.279347                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61722.437782                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59390.621690                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59390.621690                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59063.893476                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61409.992805                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61398.029211                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59063.893476                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61409.992805                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61398.029211                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1532947                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4094.376885                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           969983510                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1537043                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            631.071161                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         400583250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4094.376885                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999604                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999604                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          263                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          978                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         2415                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4          394                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1947074947                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1947074947                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    693859178                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       693859178                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    276090749                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      276090749                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10001                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10001                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         9985                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     969949927                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        969949927                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    969949927                       # number of overall hits
system.cpu.dcache.overall_hits::total       969949927                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1954107                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1954107                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       844929                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       844929                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2799036                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2799036                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2799036                       # number of overall misses
system.cpu.dcache.overall_misses::total       2799036                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  79576585056                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  79576585056                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  58758638704                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  58758638704                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       210750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       210750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 138335223760                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 138335223760                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 138335223760                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 138335223760                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    695813285                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    695813285                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10004                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10004                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         9985                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    972748963                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    972748963                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    972748963                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    972748963                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002808                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002808                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003051                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.003051                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000300                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000300                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002877                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002877                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002877                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002877                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40722.736808                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40722.736808                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69542.693770                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69542.693770                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        70250                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        70250                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49422.452502                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 49422.452502                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49422.452502                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 49422.452502                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         2414                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          988                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                54                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              92                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    44.703704                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    10.739130                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        96318                       # number of writebacks
system.cpu.dcache.writebacks::total             96318                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       489582                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       489582                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       768115                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       768115                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1257697                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1257697                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1257697                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1257697                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464525                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1464525                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        76814                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        76814                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1541339                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1541339                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1541339                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1541339                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  42200288024                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  42200288024                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4993959708                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4993959708                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47194247732                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  47194247732                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47194247732                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  47194247732                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002105                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002105                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000277                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000277                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001585                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001585                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28815.000102                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28815.000102                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65013.665582                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65013.665582                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30618.992793                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30618.992793                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30618.992793                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30618.992793                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------