path: root/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.734755                       # Number of seconds simulated
sim_ticks                                734755023500                       # Number of ticks simulated
final_tick                               734755023500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 119232                       # Simulator instruction rate (inst/s)
host_op_rate                                   162378                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               63282228                       # Simulator tick rate (ticks/s)
host_mem_usage                                 243808                       # Number of bytes of host memory used
host_seconds                                 11610.76                       # Real time elapsed on the host
sim_insts                                  1384372850                       # Number of instructions simulated
sim_ops                                    1885327602                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            205760                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          94510912                       # Number of bytes read from this memory
system.physmem.bytes_read::total             94716672                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       205760                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          205760                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230336                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230336                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3215                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1476733                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1479948                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66099                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66099                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               280039                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            128629147                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               128909186                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          280039                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             280039                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           5757478                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                5757478                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           5757478                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              280039                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           128629147                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              134666664                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1411                       # Number of system calls
system.cpu.numCycles                       1469510048                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                526868038                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          401113446                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect           36046358                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups             383398262                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                286508671                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                 60655682                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect             2811201                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          448614021                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2626557864                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   526868038                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          347164353                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     716084096                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               226374824                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              100079168                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2230                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         20420                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                 419610687                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes              12785505                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1449541071                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.542405                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.156280                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                733526710     50.60%     50.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 55834579      3.85%     54.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                113825896      7.85%     62.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 72745123      5.02%     67.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 84690661      5.84%     73.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 54721422      3.78%     76.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 33849353      2.34%     79.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 34645380      2.39%     81.67% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                265701947     18.33%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1449541071                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.358533                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.787370                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                497288026                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              79567524                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 676485575                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              11475102                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              184724844                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             81162192                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 16785                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3548614330                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 38542                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              184724844                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                535414239                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                30600962                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         541148                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 648147088                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              50112790                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             3434293747                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   117                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                4398993                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              40741019                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             1775                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          3359442434                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups           16257634697                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups      15596931258                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         660703439                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1993143706                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps               1366298728                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              50062                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          45371                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 137456980                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads           1058714008                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           577829073                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          31866160                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         36849262                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 3203795171                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               52627                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2727879490                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          26513766                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined      1318072615                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   3048733772                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          30791                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1449541071                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.881892                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.914534                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           528205619     36.44%     36.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           200385301     13.82%     50.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           218048243     15.04%     65.31% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           179845166     12.41%     77.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           155269867     10.71%     88.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5           101678601      7.01%     95.44% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            47766137      3.30%     98.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            10944186      0.76%     99.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             7397951      0.51%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1449541071                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1786371      1.87%      1.87% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  23899      0.03%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.90% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               56927453     59.70%     61.60% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              36612005     38.40%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1265692730     46.40%     46.40% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult             11246210      0.41%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   1      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     46.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.05%     46.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     46.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         6876504      0.25%     47.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         5503517      0.20%     47.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv              65      0.00%     47.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       23431459      0.86%     48.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     48.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     48.17% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            901624360     33.05%     81.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           512129355     18.77%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2727879490                       # Type of FU issued
system.cpu.iq.rate                           1.856319                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    95349728                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.034954                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6892702222                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        4416661768                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2501406306                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           134461323                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes          105324073                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     59997583                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2754068673                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                69160545                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         71273395                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    427326375                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       261567                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation      1134338                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    300833324                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            15                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              184724844                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                16014821                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1979639                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          3203920541                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           4008843                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts            1058714008                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            577829073                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              42582                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1976809                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   591                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents        1134338                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       37198169                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      9007131                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             46205300                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2628771663                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             847609803                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          99107827                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         72743                       # number of nop insts executed
system.cpu.iew.exec_refs                   1330077082                       # number of memory reference insts executed
system.cpu.iew.exec_branches                361648549                       # Number of branches executed
system.cpu.iew.exec_stores                  482467279                       # Number of stores executed
system.cpu.iew.exec_rate                     1.788876                       # Inst execution rate
system.cpu.iew.wb_sent                     2589616129                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2561403889                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1477403496                       # num instructions producing a value
system.cpu.iew.wb_consumers                2764851406                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.743033                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.534352                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts     1384383866                       # The number of committed instructions
system.cpu.commit.commitCommittedOps       1885338618                       # The number of committed instructions
system.cpu.commit.commitSquashedInsts      1318582287                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           21836                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          41567877                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1264816229                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.490603                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.207767                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    584481462     46.21%     46.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    317753060     25.12%     71.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    101743247      8.04%     79.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     79200545      6.26%     85.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     52876697      4.18%     89.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     23864362      1.89%     91.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     17162643      1.36%     93.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      9180731      0.73%     93.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     78553482      6.21%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1264816229                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1384383866                       # Number of instructions committed
system.cpu.commit.committedOps             1885338618                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      908383382                       # Number of memory references committed
system.cpu.commit.loads                     631387633                       # Number of loads committed
system.cpu.commit.membars                        9986                       # Number of memory barriers committed
system.cpu.commit.branches                  291348996                       # Number of branches committed
system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1653700675                       # Number of committed integer instructions.
system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              78553482                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   4390165307                       # The number of ROB reads
system.cpu.rob.rob_writes                  6592584661                       # The number of ROB writes
system.cpu.timesIdled                         1305443                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        19968977                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1384372850                       # Number of Instructions Simulated
system.cpu.committedOps                    1885327602                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1384372850                       # Number of Instructions Simulated
system.cpu.cpi                               1.061499                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.061499                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.942064                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.942064                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads              12961850201                       # number of integer regfile reads
system.cpu.int_regfile_writes              2434855102                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  71417921                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 51448336                       # number of floating regfile writes
system.cpu.misc_regfile_reads              4106986212                       # number of misc regfile reads
system.cpu.misc_regfile_writes               13773806                       # number of misc regfile writes
system.cpu.icache.replacements                  25589                       # number of replacements
system.cpu.icache.tagsinuse               1654.450414                       # Cycle average of tags in use
system.cpu.icache.total_refs                419572856                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  27281                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               15379.672886                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1654.450414                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.807837                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.807837                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    419577538                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       419577538                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     419577538                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        419577538                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    419577538                       # number of overall hits
system.cpu.icache.overall_hits::total       419577538                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        33149                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         33149                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        33149                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          33149                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        33149                       # number of overall misses
system.cpu.icache.overall_misses::total         33149                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    298308500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    298308500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    298308500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    298308500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    298308500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    298308500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    419610687                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    419610687                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    419610687                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    419610687                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    419610687                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    419610687                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000079                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000079                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000079                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000079                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000079                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000079                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8999.019578                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  8999.019578                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  8999.019578                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  8999.019578                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  8999.019578                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  8999.019578                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          781                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          781                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          781                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          781                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          781                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          781                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        32368                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        32368                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        32368                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        32368                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        32368                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        32368                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    180567000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    180567000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    180567000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    180567000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    180567000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    180567000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000077                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000077                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000077                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000077                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000077                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000077                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  5578.565250                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  5578.565250                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  5578.565250                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  5578.565250                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  5578.565250                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  5578.565250                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1532821                       # number of replacements
system.cpu.dcache.tagsinuse               4094.970368                       # Cycle average of tags in use
system.cpu.dcache.total_refs               1034449788                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1536917                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 673.068089                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              277219000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4094.970368                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999749                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999749                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    758296274                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       758296274                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    276114755                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      276114755                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10674                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10674                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        10437                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        10437                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data    1034411029                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total       1034411029                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data   1034411029                       # number of overall hits
system.cpu.dcache.overall_hits::total      1034411029                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2832781                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2832781                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       820923                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       820923                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      3653704                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3653704                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3653704                       # number of overall misses
system.cpu.dcache.overall_misses::total       3653704                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  91513466000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  91513466000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  28577501500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  28577501500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       115500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       115500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 120090967500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 120090967500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 120090967500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 120090967500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    761129055                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    761129055                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10677                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10677                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        10437                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        10437                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data   1038064733                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total   1038064733                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data   1038064733                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total   1038064733                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003722                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.003722                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002964                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.002964                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000281                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000281                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.003520                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.003520                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.003520                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.003520                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32305.167960                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 32305.167960                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34811.427503                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34811.427503                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        38500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32868.280381                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 32868.280381                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32868.280381                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32868.280381                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        62000                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets        15500                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       108625                       # number of writebacks
system.cpu.dcache.writebacks::total            108625                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1368436                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1368436                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       743264                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       743264                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2111700                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2111700                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2111700                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2111700                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464345                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1464345                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        77659                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        77659                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1542004                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1542004                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1542004                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1542004                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  49970798500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  49970798500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2507122500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2507122500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  52477921000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  52477921000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  52477921000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  52477921000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001924                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001924                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000280                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000280                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001485                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001485                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001485                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001485                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34125.017329                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34125.017329                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32283.734017                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32283.734017                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34032.285908                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34032.285908                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34032.285908                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34032.285908                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements               1480163                       # number of replacements
system.cpu.l2cache.tagsinuse             32703.911790                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   86402                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs               1512907                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.057110                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks  3110.119974                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     59.486457                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  29534.305360                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.094913                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.001815                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.901315                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.998044                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        24063                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        53671                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          77734                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       108625                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       108625                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         6493                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         6493                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        24063                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        60164                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           84227                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        24063                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        60164                       # number of overall hits
system.cpu.l2cache.overall_hits::total          84227                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3219                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1410673                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1413892                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         5084                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         5084                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66080                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66080                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3219                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1476753                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1479972                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3219                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1476753                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1479972                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    110372500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48394540000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  48504912500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2252380000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   2252380000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    110372500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  50646920000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  50757292500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    110372500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  50646920000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  50757292500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        27282                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1464344                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1491626                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       108625                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       108625                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         5087                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         5087                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        72573                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        72573                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        27282                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1536917                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1564199                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        27282                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1536917                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1564199                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.117990                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.963348                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.947886                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999410                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999410                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.910531                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.910531                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.117990                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.960854                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.946153                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.117990                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.960854                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.946153                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.822305                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34305.994373                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34305.953001                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.653753                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34085.653753                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.822305                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.134831                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34296.116751                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.822305                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.134831                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34296.116751                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
system.cpu.l2cache.writebacks::total            66099                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           20                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           24                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           20                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           20                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3215                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1410653                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1413868                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         5084                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         5084                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66080                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66080                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3215                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1476733                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1479948                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3215                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1476733                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1479948                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     99910500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  43827558000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  43927468500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    157604000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    157604000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2048533500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2048533500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     99910500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  45876091500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  45976002000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     99910500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  45876091500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  45976002000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.117843                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.963334                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.947870                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999410                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999410                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.910531                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.910531                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.117843                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.960841                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.946138                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.117843                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.960841                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.946138                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31076.360809                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.985782                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31069.002552                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.809625                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.809625                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31076.360809                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.935074                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.957723                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31076.360809                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.935074                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.957723                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------