path: root/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.327896                       # Number of seconds simulated
sim_ticks                                327895638000                       # Number of ticks simulated
final_tick                               327895638000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 125299                       # Simulator instruction rate (inst/s)
host_op_rate                                   154259                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               64130088                       # Simulator tick rate (ticks/s)
host_mem_usage                                 277300                       # Number of bytes of host memory used
host_seconds                                  5112.98                       # Real time elapsed on the host
sim_insts                                   640649299                       # Number of instructions simulated
sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst            266368                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          48003200                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     12980224                       # Number of bytes read from this memory
system.physmem.bytes_read::total             61249792                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       266368                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          266368                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4244096                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4244096                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4162                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             750050                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       202816                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                957028                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66314                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66314                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               812356                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            146397800                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     39586449                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               186796605                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          812356                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             812356                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          12943435                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               12943435                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          12943435                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              812356                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           146397800                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     39586449                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              199740040                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        957029                       # Number of read requests accepted
system.physmem.writeReqs                        66314                       # Number of write requests accepted
system.physmem.readBursts                      957029                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66314                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 61231232                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     18624                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4237440                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  61249856                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4244096                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      291                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      72                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               19913                       # Per bank write bursts
system.physmem.perBankRdBursts::1               19609                       # Per bank write bursts
system.physmem.perBankRdBursts::2              657177                       # Per bank write bursts
system.physmem.perBankRdBursts::3               20974                       # Per bank write bursts
system.physmem.perBankRdBursts::4               19738                       # Per bank write bursts
system.physmem.perBankRdBursts::5               20841                       # Per bank write bursts
system.physmem.perBankRdBursts::6               19544                       # Per bank write bursts
system.physmem.perBankRdBursts::7               20056                       # Per bank write bursts
system.physmem.perBankRdBursts::8               19527                       # Per bank write bursts
system.physmem.perBankRdBursts::9               20071                       # Per bank write bursts
system.physmem.perBankRdBursts::10              19467                       # Per bank write bursts
system.physmem.perBankRdBursts::11              19786                       # Per bank write bursts
system.physmem.perBankRdBursts::12              19618                       # Per bank write bursts
system.physmem.perBankRdBursts::13              21115                       # Per bank write bursts
system.physmem.perBankRdBursts::14              19501                       # Per bank write bursts
system.physmem.perBankRdBursts::15              19801                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4241                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4104                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4141                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4151                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4245                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4233                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4095                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4151                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    327895627500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  957029                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66314                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    765529                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    120932                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     14410                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      6616                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6427                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      7705                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      8957                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      9890                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      6812                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      3724                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2470                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     1588                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1057                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      621                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      585                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      627                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                      852                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1419                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     2585                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3077                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     3558                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4078                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4529                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5480                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5966                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6331                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5957                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4147                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4057                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      137                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       98                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       96                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       82                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       45                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       38                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       33                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       28                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       25                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       18                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       15                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        5                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       194181                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      337.148207                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     191.280987                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     364.158297                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          64676     33.31%     33.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        60636     31.23%     64.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        15729      8.10%     72.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         3217      1.66%     74.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         3574      1.84%     76.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         2317      1.19%     77.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         2364      1.22%     78.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023        21831     11.24%     89.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        19837     10.22%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         194181                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          3990                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean       177.226065                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       34.842577                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev     1813.556545                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-4095           3969     99.47%     99.47% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191            9      0.23%     99.70% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-12287            4      0.10%     99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-16383            2      0.05%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16384-20479            1      0.03%     99.87% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671            1      0.03%     99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-32767            2      0.05%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-40959            1      0.03%     99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::86016-90111            1      0.03%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            3990                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          3990                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.593985                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.513577                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.886226                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3332     83.51%     83.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  5      0.13%     83.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                452     11.33%     94.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 50      1.25%     96.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 19      0.48%     96.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 17      0.43%     97.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 10      0.25%     97.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 19      0.48%     97.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 12      0.30%     98.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                 15      0.38%     98.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                 16      0.40%     98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                 15      0.38%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  9      0.23%     99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  5      0.13%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  4      0.10%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  3      0.08%     99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  1      0.03%     99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  1      0.03%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34                  3      0.08%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  1      0.03%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  1      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            3990                       # Writes before turning the bus around for reads
system.physmem.totQLat                    12587538724                       # Total ticks spent queuing
system.physmem.totMemAccLat               30526376224                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4783690000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13156.72                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  31906.72                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         186.74                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          12.92                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      186.80                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       12.94                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           1.56                       # Data bus utilization in percentage
system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.10                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.87                       # Average write queue length when enqueuing
system.physmem.readRowHits                     805843                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     22921                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   84.23                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  34.60                       # Row buffer hit rate for writes
system.physmem.avgGap                       320416.15                       # Average gap between requests
system.physmem.pageHitRate                      81.01                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  934317720                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  509796375                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                6223237800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                216334800                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            21416478720                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           220944760020                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             2925699000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             253170624435                       # Total energy per rank (pJ)
system.physmem_0.averagePower              772.109253                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE     3595093339                       # Time in different power states
system.physmem_0.memoryStateTime::REF     10949120000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    313351421161                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  533690640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  291200250                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1239209400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                212706000                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            21416478720                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            88116969465                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           119441319000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             231251573475                       # Total energy per rank (pJ)
system.physmem_1.averagePower              705.261391                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   198129163855                       # Time in different power states
system.physmem_1.memoryStateTime::REF     10949120000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    118816573145                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.branchPred.lookups               174659739                       # Number of BP lookups
system.cpu.branchPred.condPredicted         119113225                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           4015668                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             96720974                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                67755362                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             70.052398                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                18785155                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1299597                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups        16716286                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits           16701799                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            14487                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted      1279501                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  673                       # Number of system calls
system.cpu.pwrStateResidencyTicks::ON    327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                        655791277                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           34353189                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      824276690                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   174659739                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          103242316                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     616975428                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 8068049                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 2182                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            17                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles         3170                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 247740649                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 12515                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          655368010                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.551156                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.253828                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                193301276     29.50%     29.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                148337850     22.63%     52.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 72946568     11.13%     63.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                240782316     36.74%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            655368010                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.266334                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.256919                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 75112130                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             236493276                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 277761287                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              61980307                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                4021010                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             20809608                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 13112                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              924575224                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              11804312                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                4021010                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                118055519                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles               135785787                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         212608                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 294557237                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             102735849                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              906541412                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               6891100                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              27959034                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2218150                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               49337765                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                 468731                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           980926815                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            4318009248                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1001835221                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          34457086                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                106148585                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               6844                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           6835                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 138814111                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            271882035                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           160585921                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           6159068                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         12159693                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  899827224                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               12580                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 860029296                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           9216848                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       111114846                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    244387313                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            426                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     655368010                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.312285                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.094624                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           192710599     29.40%     29.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           182406257     27.83%     57.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           175554116     26.79%     84.02% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            92275656     14.08%     98.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            12419071      1.89%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                2311      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       655368010                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                66605310     24.62%     24.62% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  18142      0.01%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     24.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt            636889      0.24%     24.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     24.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     24.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     24.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     24.87% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     24.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead              134121363     49.58%     74.45% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              69112589     25.55%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             413090005     48.03%     48.03% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              5187656      0.60%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     48.64% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.07%     48.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     48.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         3187674      0.37%     49.08% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         2550150      0.30%     49.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     49.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       11478194      1.33%     50.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     50.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.71% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     50.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            266665504     31.01%     81.72% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           157232585     18.28%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              860029296                       # Type of FU issued
system.cpu.iq.rate                           1.311438                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   270494293                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.314518                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         2597595667                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         980331886                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    820082893                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads            57542076                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           30641581                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     24878673                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1098503163                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                32020426                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         13986768                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     19641097                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses          121                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        18820                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores     31605425                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      1918936                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         17201                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                4021010                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                10590461                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                  6281                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           899849934                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             271882035                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            160585921                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               6840                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    959                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  3423                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          18820                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3295129                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3290187                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              6585316                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             850173752                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             263373804                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           9855544                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         10130                       # number of nop insts executed
system.cpu.iew.exec_refs                    416063188                       # number of memory reference insts executed
system.cpu.iew.exec_branches                143381327                       # Number of branches executed
system.cpu.iew.exec_stores                  152689384                       # Number of stores executed
system.cpu.iew.exec_rate                     1.296409                       # Inst execution rate
system.cpu.iew.wb_sent                      846297655                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     844961566                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 487343298                       # num instructions producing a value
system.cpu.iew.wb_consumers                 808106626                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.288461                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.603068                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts       103169122                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           4002654                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    640787345                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.230876                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.070419                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    350447626     54.69%     54.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    137241088     21.42%     76.11% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     51341072      8.01%     84.12% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     28220230      4.40%     88.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     14380949      2.24%     90.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     14774505      2.31%     93.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      7871971      1.23%     94.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      6561231      1.02%     95.33% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     29948673      4.67%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    640787345                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      381221434                       # Number of memory references committed
system.cpu.commit.loads                     252240938                       # Number of loads committed
system.cpu.commit.membars                        5740                       # Number of memory barriers committed
system.cpu.commit.branches                  137364860                       # Number of branches committed
system.cpu.commit.fp_insts                   24239771                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 682251399                       # Number of committed integer instructions.
system.cpu.commit.function_calls             19275340                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        385756794     48.91%     48.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         5173441      0.66%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd       637528      0.08%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp      3187668      0.40%     50.05% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt      2550131      0.32%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc     10203074      1.29%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       252240938     31.98%     83.65% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
system.cpu.commit.bw_lim_events              29948673                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1502729113                       # The number of ROB reads
system.cpu.rob.rob_writes                  1798382436                       # The number of ROB writes
system.cpu.timesIdled                           10485                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          423267                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.023635                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.023635                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.976910                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.976910                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                868461212                       # number of integer regfile reads
system.cpu.int_regfile_writes               500699124                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  30616064                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 22959493                       # number of floating regfile writes
system.cpu.cc_regfile_reads                3322386264                       # number of cc regfile reads
system.cpu.cc_regfile_writes                369207629                       # number of cc regfile writes
system.cpu.misc_regfile_reads               606832888                       # number of misc regfile reads
system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           2756458                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.912011                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           371050492                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2756970                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            134.586336                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         274880000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.912011                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999828                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999828                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          167                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         751746846                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        751746846                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    243126867                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       243126867                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    127907624                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      127907624                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         3157                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          3157                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         5738                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         5738                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     371034491                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        371034491                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    371037648                       # number of overall hits
system.cpu.dcache.overall_hits::total       371037648                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2401310                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2401310                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1043853                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1043853                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          647                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          647                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      3445163                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3445163                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3445810                       # number of overall misses
system.cpu.dcache.overall_misses::total       3445810                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  69278020000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  69278020000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data   9882341350                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   9882341350                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       168500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       168500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  79160361350                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  79160361350                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  79160361350                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  79160361350                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    245528177                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    245528177                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         3804                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         3804                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5741                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         5741                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    374479654                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    374479654                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    374483458                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    374483458                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009780                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.009780                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008095                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.008095                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.170084                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.170084                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009200                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009200                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009202                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009202                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28850.094324                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28850.094324                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9467.177227                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  9467.177227                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56166.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56166.666667                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22977.247042                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 22977.247042                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22972.932736                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 22972.932736                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       322646                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets            4628                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    69.716076                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      2756458                       # number of writebacks
system.cpu.dcache.writebacks::total           2756458                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       365828                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       365828                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       322833                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       322833                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data       688661                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total       688661                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data       688661                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total       688661                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035482                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      2035482                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       721020                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       721020                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          642                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          642                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2756502                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2756502                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2757144                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2757144                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  64102936000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  64102936000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5940509850                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5940509850                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5561000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5561000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  70043445850                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  70043445850                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  70049006850                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  70049006850                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.008290                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.008290                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005591                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005591                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168770                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168770                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007361                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.007361                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007363                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.007363                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31492.755033                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31492.755033                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8239.036157                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8239.036157                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8661.993769                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8661.993769                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25410.264839                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25410.264839                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25406.365010                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25406.365010                       # average overall mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements           1979522                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.874726                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           245757404                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           1980032                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            124.117895                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle         264413500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.874726                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997802                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997802                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          111                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          335                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         497461440                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        497461440                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    245757408                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       245757408                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     245757408                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        245757408                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    245757408                       # number of overall hits
system.cpu.icache.overall_hits::total       245757408                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      1983209                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       1983209                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      1983209                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        1983209                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      1983209                       # number of overall misses
system.cpu.icache.overall_misses::total       1983209                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  16177953926                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  16177953926                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  16177953926                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  16177953926                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  16177953926                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  16177953926                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    247740617                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    247740617                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    247740617                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    247740617                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    247740617                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    247740617                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008005                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.008005                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.008005                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.008005                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.008005                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.008005                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8157.462943                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  8157.462943                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  8157.462943                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  8157.462943                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  8157.462943                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  8157.462943                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        75964                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          122                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              2856                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    26.598039                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    24.400000                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks      1979522                       # number of writebacks
system.cpu.icache.writebacks::total           1979522                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3001                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3001                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3001                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3001                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3001                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3001                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1980208                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      1980208                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      1980208                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      1980208                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      1980208                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      1980208                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  15149087440                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  15149087440                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  15149087440                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  15149087440                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  15149087440                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  15149087440                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.007993                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.007993                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.007993                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.007993                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.007993                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.007993                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7650.250600                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7650.250600                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7650.250600                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  7650.250600                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7650.250600                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  7650.250600                       # average overall mshr miss latency
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.prefetcher.num_hwpf_issued      1350340                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      1355050                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         4121                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage      4790102                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements           297234                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16098.063865                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3815891                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           313429                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            12.174658                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 15670.505298                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   427.558566                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.956452                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.026096                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.982548                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          418                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        15777                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            6                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           61                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3          259                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4           92                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          412                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1577                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3842                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         9849                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.025513                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.962952                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        145585225                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       145585225                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.WritebackDirty_hits::writebacks       735545                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total       735545                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks      3357840                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total      3357840                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       718742                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       718742                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1975871                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      1975871                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1286733                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1286733                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst      1975871                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2005475                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         3981346                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      1975871                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2005475                       # number of overall hits
system.cpu.l2cache.overall_hits::total        3981346                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data          174                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          174                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2104                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2104                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         4164                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         4164                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       749391                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       749391                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4164                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       751495                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        755659                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4164                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       751495                       # number of overall misses
system.cpu.l2cache.overall_misses::total       755659                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    179065000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    179065000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    319741500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    319741500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  52681851500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  52681851500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    319741500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  52860916500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  53180658000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    319741500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  52860916500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  53180658000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks       735545                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total       735545                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks      3357840                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total      3357840                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          174                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          174                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       720846                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       720846                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1980035                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      1980035                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2036124                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      2036124                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      1980035                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2756970                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      4737005                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      1980035                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2756970                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      4737005                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002919                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.002919                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.002103                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.002103                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.368048                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.368048                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.002103                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.272580                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.159523                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.002103                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.272580                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.159523                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85106.939163                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85106.939163                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76787.103746                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76787.103746                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70299.551903                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70299.551903                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76787.103746                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70341.008922                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70376.529625                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76787.103746                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70341.008922                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70376.529625                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.unused_prefetches             3678                       # number of HardPF blocks evicted w/o reference
system.cpu.l2cache.writebacks::writebacks        66314                       # number of writebacks
system.cpu.l2cache.writebacks::total            66314                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          742                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total          742                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          703                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          703                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         1445                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         1446                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         1445                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         1446                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202914                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       202914                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          174                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          174                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1362                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1362                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         4163                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         4163                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       748688                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       748688                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4163                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       750050                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       754213                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4163                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       750050                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202914                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       957127                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  16536801285                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  16536801285                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2630000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2630000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    133214500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    133214500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    294714000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    294714000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  48154340500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  48154340500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    294714000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  48287555000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  48582269000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    294714000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  48287555000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  16536801285                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  65119070285                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001889                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001889                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.002102                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.002102                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.367703                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.367703                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.002102                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.272056                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.159217                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.002102                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.272056                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.202053                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 81496.600949                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15114.942529                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15114.942529                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97808.002937                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97808.002937                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70793.658419                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70793.658419                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64318.301482                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64318.301482                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70793.658419                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64379.114726                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64414.520832                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70793.658419                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64379.114726                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68035.976715                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      9473332                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      4736180                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests       642769                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops           98                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops           97                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            1                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp       4016330                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       801859                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean      4000435                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       230920                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       258553                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq          174                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          174                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       720846                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       720846                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      1980208                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      2036124                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5939763                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8270746                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          14210509                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    253411520                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    352859392                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          606270912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      555960                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic               4255168                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples      5293139                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.121491                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.326697                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            4650072     87.85%     87.85% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             643066     12.15%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  1      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        5293139                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     9472646000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    2970310996                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    4135552978                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
system.membus.snoop_filter.tot_requests       1254437                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests       940010                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 327895638000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp             955666                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        66314                       # Transaction distribution
system.membus.trans_dist::CleanEvict           230920                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              174                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1362                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1362                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        955667                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2211465                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                2211465                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     65493888                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                65493888                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples            957203                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  957203    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              957203                       # Request fanout histogram
system.membus.reqLayer0.occupancy          1755655982                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         5035261795                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)

---------- End Simulation Statistics   ----------