path: root/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.735463                       # Number of seconds simulated
sim_ticks                                735462942500                       # Number of ticks simulated
final_tick                               735462942500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 115593                       # Simulator instruction rate (inst/s)
host_op_rate                                   157422                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               61409842                       # Simulator tick rate (ticks/s)
host_mem_usage                                 243732                       # Number of bytes of host memory used
host_seconds                                 11976.30                       # Real time elapsed on the host
sim_insts                                  1384378705                       # Number of instructions simulated
sim_ops                                    1885333457                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            209152                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          94513152                       # Number of bytes read from this memory
system.physmem.bytes_read::total             94722304                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       209152                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          209152                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3268                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1476768                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1480036                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               284381                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            128508381                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               128792762                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          284381                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             284381                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           5751849                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                5751849                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           5751849                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              284381                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           128508381                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              134544612                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1411                       # Number of system calls
system.cpu.numCycles                       1470925886                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                526944807                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          400998639                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect           36103831                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups             389912593                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                290078755                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                 59371448                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect             2810327                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          451184041                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2630280787                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   526944807                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          349450203                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     714901139                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               225817309                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              101657894                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                 2270                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         20337                       # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines                 420935290                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes              11687737                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1451892883                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.541647                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.159630                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                737052267     50.76%     50.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 55648987      3.83%     54.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                113021811      7.78%     62.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 71058557      4.89%     67.28% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 83474414      5.75%     73.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 55105836      3.80%     76.82% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 35245314      2.43%     79.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 35853884      2.47%     81.72% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                265431813     18.28%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1451892883                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.358240                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.788180                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                498609504                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              80967892                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 677644967                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              10558484                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              184112036                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             82169847                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 15539                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3562988403                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 34450                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              184112036                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                537763866                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                32181538                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         530906                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 647549947                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              49754590                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             3439334544                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   240                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                4507727                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              40704108                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents             1637                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          3357877059                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups           16273276362                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups      15612337004                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         660939358                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1993153074                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps               1364723985                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              50374                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          45755                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 138448530                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads           1057693537                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           579697033                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          32301976                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         40224751                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 3204253855                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               55204                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2728539607                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          26296633                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined      1318520975                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   3049786617                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved          32197                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1451892883                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.879298                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.913242                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           529391229     36.46%     36.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           201881649     13.90%     50.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           217086646     14.95%     65.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           180698536     12.45%     77.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           155303824     10.70%     88.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5           101627119      7.00%     95.46% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            47687061      3.28%     98.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            10818751      0.75%     99.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             7398068      0.51%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1451892883                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 1769730      1.85%      1.85% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  23897      0.03%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.88% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               57017691     59.74%     61.62% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              36624161     38.38%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1267852875     46.47%     46.47% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult             11249841      0.41%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   1      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     46.88% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.05%     46.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     46.93% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         6876502      0.25%     47.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         5509242      0.20%     47.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv              10      0.00%     47.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       23422716      0.86%     48.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     48.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.24% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     48.24% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            900241539     32.99%     81.23% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           512011592     18.77%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2728539607                       # Type of FU issued
system.cpu.iq.rate                           1.854981                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    95435479                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.034977                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6896111029                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        4417455828                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2500265065                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           134593180                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes          105438972                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     60061785                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2754719800                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                69255286                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         70868561                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    426304733                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses       264948                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation      1116073                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    302700113                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            2                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked            13                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              184112036                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                17217570                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               2222077                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          3204383976                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           3801477                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts            1057693537                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            579697033                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              44065                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                2220604                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                   655                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents        1116073                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       37419443                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      9018722                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             46438165                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2627591050                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             846492275                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts         100948557                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         74917                       # number of nop insts executed
system.cpu.iew.exec_refs                   1329282286                       # number of memory reference insts executed
system.cpu.iew.exec_branches                361424797                       # Number of branches executed
system.cpu.iew.exec_stores                  482790011                       # Number of stores executed
system.cpu.iew.exec_rate                     1.786352                       # Inst execution rate
system.cpu.iew.wb_sent                     2588656133                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2560326850                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1477151291                       # num instructions producing a value
system.cpu.iew.wb_consumers                2761912490                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.740623                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.534829                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts      1319039983                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           23007                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          41626374                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1267780849                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.487122                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.205349                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    586908423     46.29%     46.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    318188211     25.10%     71.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    101915381      8.04%     79.43% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     79184752      6.25%     85.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     52930899      4.18%     89.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     24002778      1.89%     91.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     17056118      1.35%     93.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      9057246      0.71%     93.81% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     78537041      6.19%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1267780849                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1384389721                       # Number of instructions committed
system.cpu.commit.committedOps             1885344473                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      908385724                       # Number of memory references committed
system.cpu.commit.loads                     631388804                       # Number of loads committed
system.cpu.commit.membars                        9986                       # Number of memory barriers committed
system.cpu.commit.branches                  291350167                       # Number of branches committed
system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1653705359                       # Number of committed integer instructions.
system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              78537041                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   4393609919                       # The number of ROB reads
system.cpu.rob.rob_writes                  6592898385                       # The number of ROB writes
system.cpu.timesIdled                         1319009                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        19033003                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1384378705                       # Number of Instructions Simulated
system.cpu.committedOps                    1885333457                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1384378705                       # Number of Instructions Simulated
system.cpu.cpi                               1.062517                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.062517                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.941161                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.941161                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads              12954963873                       # number of integer regfile reads
system.cpu.int_regfile_writes              2433899431                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  71453474                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 51512029                       # number of floating regfile writes
system.cpu.misc_regfile_reads              4110345957                       # number of misc regfile reads
system.cpu.misc_regfile_writes               13776148                       # number of misc regfile writes
system.cpu.icache.replacements                  27727                       # number of replacements
system.cpu.icache.tagsinuse               1657.357291                       # Cycle average of tags in use
system.cpu.icache.total_refs                420895339                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  29422                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               14305.463225                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1657.357291                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.809256                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.809256                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    420900012                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       420900012                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     420900012                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        420900012                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    420900012                       # number of overall hits
system.cpu.icache.overall_hits::total       420900012                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        35278                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         35278                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        35278                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          35278                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        35278                       # number of overall misses
system.cpu.icache.overall_misses::total         35278                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    347510000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    347510000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    347510000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    347510000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    347510000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    347510000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    420935290                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    420935290                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    420935290                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    420935290                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    420935290                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    420935290                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000084                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000084                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000084                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000084                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000084                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000084                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  9850.615114                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  9850.615114                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  9850.615114                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  9850.615114                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  9850.615114                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  9850.615114                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst          933                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total          933                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst          933                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total          933                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst          933                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total          933                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        34345                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        34345                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        34345                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        34345                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        34345                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        34345                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    217293500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    217293500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    217293500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    217293500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    217293500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    217293500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000082                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000082                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000082                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000082                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000082                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000082                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  6326.787014                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  6326.787014                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  6326.787014                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  6326.787014                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  6326.787014                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  6326.787014                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1532802                       # number of replacements
system.cpu.dcache.tagsinuse               4094.906416                       # Cycle average of tags in use
system.cpu.dcache.total_refs               1033702432                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1536898                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 672.590134                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              306710000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4094.906416                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999733                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999733                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    757546654                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       757546654                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    276115180                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      276115180                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        11970                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        11970                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        11608                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        11608                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data    1033661834                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total       1033661834                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data   1033661834                       # number of overall hits
system.cpu.dcache.overall_hits::total      1033661834                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      2867388                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       2867388                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       820498                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       820498                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            6                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            6                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      3687886                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        3687886                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      3687886                       # number of overall misses
system.cpu.dcache.overall_misses::total       3687886                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  99520769500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  99520769500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  33963338500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  33963338500                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       216500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       216500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 133484108000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 133484108000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 133484108000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 133484108000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    760414042                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    760414042                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11976                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        11976                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        11608                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        11608                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data   1037349720                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total   1037349720                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data   1037349720                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total   1037349720                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003771                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.003771                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002963                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.002963                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000501                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000501                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.003555                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.003555                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.003555                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.003555                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34707.814045                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34707.814045                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41393.566468                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41393.566468                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36083.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 36083.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36195.291286                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 36195.291286                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36195.291286                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36195.291286                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        58500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               3                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets        19500                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       108638                       # number of writebacks
system.cpu.dcache.writebacks::total            108638                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1403027                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      1403027                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       743038                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       743038                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            6                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            6                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      2146065                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      2146065                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      2146065                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      2146065                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464361                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1464361                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        77460                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        77460                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1541821                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1541821                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1541821                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1541821                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  50337065001                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  50337065001                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2525124500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2525124500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  52862189501                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  52862189501                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  52862189501                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  52862189501                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001926                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001926                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000280                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000280                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001486                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001486                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001486                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001486                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34374.764830                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34374.764830                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32599.076943                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32599.076943                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34285.555522                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34285.555522                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34285.555522                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34285.555522                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements               1480261                       # number of replacements
system.cpu.l2cache.tagsinuse             32698.232813                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                   88469                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs               1513005                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.058472                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks  3127.449947                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     61.048059                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  29509.734807                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.095442                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.001863                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.900566                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.997871                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        26144                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        53654                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          79798                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       108638                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       108638                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         6457                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         6457                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        26144                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        60111                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           86255                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        26144                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        60111                       # number of overall hits
system.cpu.l2cache.overall_hits::total          86255                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3279                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1410706                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1413985                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         4920                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         4920                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66081                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66081                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3279                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      1476787                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       1480066                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3279                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      1476787                       # number of overall misses
system.cpu.l2cache.overall_misses::total      1480066                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    116051500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48793887000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  48909938500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2274851500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   2274851500                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    116051500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  51068738500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  51184790000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    116051500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  51068738500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  51184790000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        29423                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1464360                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1493783                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       108638                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       108638                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4923                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         4923                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        72538                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        72538                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        29423                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1536898                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1566321                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        29423                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1536898                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1566321                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.111443                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.963360                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.946580                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999391                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999391                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.910985                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.910985                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111443                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.960888                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.944931                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111443                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.960888                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.944931                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35392.345227                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34588.274949                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34590.139570                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34425.197863                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34425.197863                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35392.345227                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34580.977826                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 34582.775363                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35392.345227                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34580.977826                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 34582.775363                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           11                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           19                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           30                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           11                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           19                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           30                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           11                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           19                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           30                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3268                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1410687                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1413955                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4920                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         4920                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66081                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66081                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3268                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      1476768                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      1480036                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3268                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      1476768                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      1480036                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    105473000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  44226810500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  44332283500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    152520000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    152520000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2049208000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2049208000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    105473000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  46276018500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  46381491500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    105473000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  46276018500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  46381491500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.111070                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.963347                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.946560                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999391                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999391                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.910985                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.910985                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.111070                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.960876                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.944912                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.111070                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.960876                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.944912                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32274.479804                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.256870                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.390667                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.547661                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.547661                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32274.479804                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31336.011141                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.083330                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32274.479804                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31336.011141                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.083330                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------