path: root/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.624868                       # Number of seconds simulated
sim_ticks                                624867585500                       # Number of ticks simulated
final_tick                               624867585500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 118271                       # Simulator instruction rate (inst/s)
host_op_rate                                   161069                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               53384157                       # Simulator tick rate (ticks/s)
host_mem_usage                                 298364                       # Number of bytes of host memory used
host_seconds                                 11705.11                       # Real time elapsed on the host
sim_insts                                  1384379060                       # Number of instructions simulated
sim_ops                                    1885333812                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            155584                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          30242752                       # Number of bytes read from this memory
system.physmem.bytes_read::total             30398336                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       155584                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          155584                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2431                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             472543                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                474974                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               248987                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             48398657                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                48647644                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          248987                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             248987                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           6769869                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6769869                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           6769869                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              248987                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            48398657                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               55417514                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        474974                       # Total number of read requests seen
system.physmem.writeReqs                        66098                       # Total number of write requests seen
system.physmem.cpureqs                         545402                       # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead                     30398336                       # Total number of bytes read from memory
system.physmem.bytesWritten                   4230272                       # Total number of bytes written to memory
system.physmem.bytesConsumedRd               30398336                       # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr                4230272                       # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ                      146                       # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite               4330                       # Reqs where no action is needed
system.physmem.perBankRdReqs::0                 29668                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::1                 29687                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::2                 29628                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::3                 29545                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::4                 29653                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::5                 29623                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::6                 29618                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::7                 29734                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::8                 29744                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::9                 29769                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::10                29790                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::11                29857                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::12                29669                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::13                29606                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::14                29627                       # Track reads on a per bank basis
system.physmem.perBankRdReqs::15                29610                       # Track reads on a per bank basis
system.physmem.perBankWrReqs::0                  4129                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::1                  4141                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::2                  4096                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::3                  4102                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::4                  4129                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::5                  4105                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::6                  4104                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::7                  4141                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::8                  4162                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::9                  4162                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::10                 4162                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::11                 4159                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::12                 4135                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::13                 4135                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::14                 4108                       # Track writes on a per bank basis
system.physmem.perBankWrReqs::15                 4128                       # Track writes on a per bank basis
system.physmem.numRdRetry                           0                       # Number of times rd buffer was full causing retry
system.physmem.numWrRetry                           0                       # Number of times wr buffer was full causing retry
system.physmem.totGap                    624867513500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Categorize read packet sizes
system.physmem.readPktSize::1                       0                       # Categorize read packet sizes
system.physmem.readPktSize::2                       0                       # Categorize read packet sizes
system.physmem.readPktSize::3                       0                       # Categorize read packet sizes
system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
system.physmem.readPktSize::6                  474974                       # Categorize read packet sizes
system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
system.physmem.writePktSize::0                      0                       # categorize write packet sizes
system.physmem.writePktSize::1                      0                       # categorize write packet sizes
system.physmem.writePktSize::2                      0                       # categorize write packet sizes
system.physmem.writePktSize::3                      0                       # categorize write packet sizes
system.physmem.writePktSize::4                      0                       # categorize write packet sizes
system.physmem.writePktSize::5                      0                       # categorize write packet sizes
system.physmem.writePktSize::6                  66098                       # categorize write packet sizes
system.physmem.writePktSize::7                      0                       # categorize write packet sizes
system.physmem.writePktSize::8                      0                       # categorize write packet sizes
system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::6                 4330                       # categorize neither packet sizes
system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
system.physmem.rdQLenPdf::0                    407769                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     66657                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       297                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        83                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        18                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2874                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     2873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     2873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     2873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.totQLat                     3316258619                       # Total cycles spent in queuing delays
system.physmem.totMemAccLat               18090208619                       # Sum of mem lat for all requests
system.physmem.totBusLat                   1899312000                       # Total cycles spent in databus access
system.physmem.totBankLat                 12874638000                       # Total cycles spent in bank access
system.physmem.avgQLat                        6984.13                       # Average queueing delay per request
system.physmem.avgBankLat                    27114.32                       # Average bank access latency per request
system.physmem.avgBusLat                      4000.00                       # Average bus latency per request
system.physmem.avgMemAccLat                  38098.45                       # Average memory access latency
system.physmem.avgRdBW                          48.65                       # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW                           6.77                       # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW                  48.65                       # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW                   6.77                       # Average consumed write bandwidth in MB/s
system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
system.physmem.busUtil                           0.35                       # Data bus utilization in percentage
system.physmem.avgRdQLen                         0.03                       # Average read queue length over time
system.physmem.avgWrQLen                        17.43                       # Average write queue length over time
system.physmem.readRowHits                     249202                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     48033                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   52.48                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  72.67                       # Row buffer hit rate for writes
system.physmem.avgGap                      1154869.43                       # Average gap between requests
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1411                       # Number of system calls
system.cpu.numCycles                       1249735172                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.BPredUnit.lookups                439117025                       # Number of BP lookups
system.cpu.BPredUnit.condPredicted          350578524                       # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect           30630316                       # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups             248764319                       # Number of BTB lookups
system.cpu.BPredUnit.BTBHits                227490785                       # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS                 52186990                       # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect             2806187                       # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles          354123352                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2285928065                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   439117025                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          279677775                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     600707462                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               157912293                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              133000859                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  565                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         11147                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           82                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 333825475                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes              10767149                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1215073364                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.587868                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.187266                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                614410423     50.57%     50.57% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 42578199      3.50%     54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 95045800      7.82%     61.89% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 56224969      4.63%     66.52% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 72457573      5.96%     72.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 42599927      3.51%     75.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 31039765      2.55%     78.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 31697654      2.61%     81.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                229019054     18.85%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1215073364                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.351368                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.829130                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                403820359                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             105461627                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 561742218                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              16831582                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              127217578                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             44615078                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 13114                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3041090435                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 27022                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              127217578                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                439577665                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                35450988                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         444214                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 540789818                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              71593101                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2966286071                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    77                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                4807554                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              56267627                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands          2940514356                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups           14121260893                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups      13550785312                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups         570475581                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1993153642                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                947360714                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              22542                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          20019                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 191397273                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            972715984                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           490205592                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          36288460                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         40771047                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2804297042                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               31006                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2436370950                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          13311855                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       906440094                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   2354573703                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           7928                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1215073364                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.005123                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.874281                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           379121475     31.20%     31.20% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           183370974     15.09%     46.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           203148367     16.72%     63.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           169783138     13.97%     76.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           132635579     10.92%     87.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            93723777      7.71%     95.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            37883178      3.12%     98.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            12361449      1.02%     99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             3045427      0.25%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1215073364                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  714606      0.82%      0.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  24380      0.03%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               55143304     62.90%     63.75% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              31782308     36.25%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1107294192     45.45%     45.45% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult             11224034      0.46%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.91% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     45.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.97% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         6876476      0.28%     46.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         5502357      0.23%     46.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     46.47% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       23404551      0.96%     47.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.43% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.43% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            838357967     34.41%     81.84% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           442336083     18.16%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2436370950                       # Type of FU issued
system.cpu.iq.rate                           1.949510                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    87664598                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.035982                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6066277406                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3628118286                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2252998417                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           122514311                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           82717236                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     56437909                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2460715459                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                63320089                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         84361835                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    341327109                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         8250                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation      1428808                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    213208601                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            6                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           221                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              127217578                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                13751124                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1562188                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2804340477                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1409393                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             972715984                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            490205592                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              19935                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1558593                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  2526                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents        1428808                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       32521161                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      1512713                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             34033874                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2362219907                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             792646926                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          74151043                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         12429                       # number of nop insts executed
system.cpu.iew.exec_refs                   1216288233                       # number of memory reference insts executed
system.cpu.iew.exec_branches                322226431                       # Number of branches executed
system.cpu.iew.exec_stores                  423641307                       # Number of stores executed
system.cpu.iew.exec_rate                     1.890176                       # Inst execution rate
system.cpu.iew.wb_sent                     2335115057                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2309436326                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1347701281                       # num instructions producing a value
system.cpu.iew.wb_consumers                2523709653                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.847941                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.534016                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       918995782                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           23078                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          30617997                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1087855788                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.733083                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.398277                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    447553397     41.14%     41.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    288592120     26.53%     67.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     95115403      8.74%     76.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     70228058      6.46%     82.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     46464545      4.27%     87.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     22184894      2.04%     89.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     15849617      1.46%     90.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     10984656      1.01%     91.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     90883098      8.35%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1087855788                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1384390076                       # Number of instructions committed
system.cpu.commit.committedOps             1885344828                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      908385866                       # Number of memory references committed
system.cpu.commit.loads                     631388875                       # Number of loads committed
system.cpu.commit.membars                        9986                       # Number of memory barriers committed
system.cpu.commit.branches                  299636089                       # Number of branches committed
system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1653705643                       # Number of committed integer instructions.
system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              90883098                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   3801294955                       # The number of ROB reads
system.cpu.rob.rob_writes                  5735909866                       # The number of ROB writes
system.cpu.timesIdled                          353133                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        34661808                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1384379060                       # Number of Instructions Simulated
system.cpu.committedOps                    1885333812                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1384379060                       # Number of Instructions Simulated
system.cpu.cpi                               0.902741                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.902741                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.107738                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.107738                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads              11770471325                       # number of integer regfile reads
system.cpu.int_regfile_writes              2224868034                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  68796296                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 49549961                       # number of floating regfile writes
system.cpu.misc_regfile_reads              1363964167                       # number of misc regfile reads
system.cpu.misc_regfile_writes               13776290                       # number of misc regfile writes
system.cpu.icache.replacements                  22546                       # number of replacements
system.cpu.icache.tagsinuse               1642.542137                       # Cycle average of tags in use
system.cpu.icache.total_refs                333790581                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                  24232                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               13774.784624                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst    1642.542137                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.802023                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.802023                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst    333794637                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       333794637                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     333794637                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        333794637                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    333794637                       # number of overall hits
system.cpu.icache.overall_hits::total       333794637                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        30836                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         30836                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        30836                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          30836                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        30836                       # number of overall misses
system.cpu.icache.overall_misses::total         30836                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    469688998                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    469688998                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    469688998                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    469688998                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    469688998                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    469688998                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    333825473                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    333825473                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    333825473                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    333825473                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    333825473                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    333825473                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000092                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000092                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000092                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000092                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000092                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000092                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15231.839344                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 15231.839344                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15231.839344                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 15231.839344                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15231.839344                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15231.839344                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1009                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                29                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    34.793103                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2272                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2272                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2272                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2272                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2272                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2272                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        28564                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        28564                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        28564                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        28564                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        28564                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        28564                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    379117998                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    379117998                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    379117998                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    379117998                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    379117998                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    379117998                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000086                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000086                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000086                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13272.580801                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13272.580801                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13272.580801                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13272.580801                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13272.580801                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13272.580801                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                1532987                       # number of replacements
system.cpu.dcache.tagsinuse               4094.606879                       # Cycle average of tags in use
system.cpu.dcache.total_refs                970022641                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                1537083                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 631.080196                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle              335185000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4094.606879                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999660                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999660                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    693885026                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       693885026                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    276101075                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      276101075                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        11981                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        11981                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        11679                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        11679                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     969986101                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        969986101                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    969986101                       # number of overall hits
system.cpu.dcache.overall_hits::total       969986101                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1953380                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1953380                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       834603                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       834603                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2787983                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2787983                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2787983                       # number of overall misses
system.cpu.dcache.overall_misses::total       2787983                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  67369161000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  67369161000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  39954942470                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  39954942470                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       199000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       199000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 107324103470                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 107324103470                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 107324103470                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 107324103470                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    695838406                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    695838406                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11984                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        11984                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        11679                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        11679                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    972774084                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    972774084                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    972774084                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    972774084                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002807                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002807                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003014                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.003014                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000250                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000250                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002866                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002866                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002866                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002866                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34488.507612                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34488.507612                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47872.991674                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 47872.991674                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66333.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66333.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38495.250319                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 38495.250319                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38495.250319                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 38495.250319                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         1740                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          681                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                55                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              87                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.636364                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     7.827586                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        96322                       # number of writebacks
system.cpu.dcache.writebacks::total             96322                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       488810                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       488810                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       757757                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       757757                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1246567                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1246567                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1246567                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1246567                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464570                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1464570                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        76846                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        76846                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1541416                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1541416                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1541416                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1541416                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  37884239500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  37884239500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3478488500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   3478488500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  41362728000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  41362728000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  41362728000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  41362728000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002105                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002105                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000277                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000277                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001585                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001585                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001585                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25867.141550                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25867.141550                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45265.706738                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45265.706738                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26834.240724                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26834.240724                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26834.240724                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26834.240724                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                442193                       # number of replacements
system.cpu.l2cache.tagsinuse             32688.524201                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 1109720                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                474940                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  2.336548                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks  1294.928331                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     48.758922                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  31344.836948                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.039518                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.001488                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.956569                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.997575                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst        21799                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1058077                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1079876                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks        96322                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total        96322                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         6441                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         6441                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        21799                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1064518                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1086317                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        21799                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1064518                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1086317                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2433                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       406491                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       408924                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         4330                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         4330                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66074                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66074                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2433                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       472565                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        474998                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2433                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       472565                       # number of overall misses
system.cpu.l2cache.overall_misses::total       474998                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    128014500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  25837930500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  25965945000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3242870000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   3242870000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    128014500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  29080800500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  29208815000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    128014500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  29080800500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  29208815000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        24232                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1464568                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1488800                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks        96322                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total        96322                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4333                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         4333                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        72515                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        72515                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        24232                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1537083                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1561315                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        24232                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1537083                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1561315                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.100404                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.277550                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.274667                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999308                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999308                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911177                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.911177                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.100404                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.307443                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.304229                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.100404                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.307443                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.304229                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52615.906289                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63563.351956                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 63498.217273                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49079.365560                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49079.365560                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52615.906289                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61538.202152                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 61492.501021                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52615.906289                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61538.202152                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 61492.501021                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           22                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           24                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           22                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           22                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           24                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2431                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406469                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       408900                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4330                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         4330                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66074                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66074                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2431                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       472543                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       474974                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2431                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       472543                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       474974                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     97294812                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  20693796850                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  20791091662                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     43304330                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     43304330                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2390499504                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2390499504                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     97294812                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23084296354                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23181591166                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     97294812                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23084296354                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23181591166                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.100322                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.277535                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.274651                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999308                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999308                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911177                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911177                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.100322                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.307428                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.304214                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.100322                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.307428                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.304214                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.547100                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50911.131845                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50846.396826                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36179.124981                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36179.124981                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.547100                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48851.207941                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48806.021311                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.547100                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48851.207941                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48806.021311                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------