path: root/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.409399                       # Number of seconds simulated
sim_ticks                                409399480000                       # Number of ticks simulated
final_tick                               409399480000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  92444                       # Simulator instruction rate (inst/s)
host_op_rate                                   113811                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               59075206                       # Simulator tick rate (ticks/s)
host_mem_usage                                 244496                       # Number of bytes of host memory used
host_seconds                                  6930.14                       # Real time elapsed on the host
sim_insts                                   640649298                       # Number of instructions simulated
sim_ops                                     788724957                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            232192                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7025088                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     12938560                       # Number of bytes read from this memory
system.physmem.bytes_read::total             20195840                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       232192                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          232192                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4244864                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4244864                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3628                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             109767                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       202165                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                315560                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66326                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66326                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               567153                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             17159494                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     31603753                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                49330400                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          567153                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             567153                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          10368513                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               10368513                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          10368513                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              567153                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            17159494                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     31603753                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               59698913                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        315560                       # Number of read requests accepted
system.physmem.writeReqs                        66326                       # Number of write requests accepted
system.physmem.readBursts                      315560                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66326                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 20177344                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     18496                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4238912                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  20195840                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4244864                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      289                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      63                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             16                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               19910                       # Per bank write bursts
system.physmem.perBankRdBursts::1               19474                       # Per bank write bursts
system.physmem.perBankRdBursts::2               19822                       # Per bank write bursts
system.physmem.perBankRdBursts::3               19845                       # Per bank write bursts
system.physmem.perBankRdBursts::4               19720                       # Per bank write bursts
system.physmem.perBankRdBursts::5               20103                       # Per bank write bursts
system.physmem.perBankRdBursts::6               19622                       # Per bank write bursts
system.physmem.perBankRdBursts::7               19424                       # Per bank write bursts
system.physmem.perBankRdBursts::8               19577                       # Per bank write bursts
system.physmem.perBankRdBursts::9               19501                       # Per bank write bursts
system.physmem.perBankRdBursts::10              19475                       # Per bank write bursts
system.physmem.perBankRdBursts::11              19731                       # Per bank write bursts
system.physmem.perBankRdBursts::12              19558                       # Per bank write bursts
system.physmem.perBankRdBursts::13              20043                       # Per bank write bursts
system.physmem.perBankRdBursts::14              19546                       # Per bank write bursts
system.physmem.perBankRdBursts::15              19920                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4269                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4104                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4141                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4150                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4244                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4227                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4154                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    409399425500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  315560                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66326                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    122658                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    117599                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     14107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      6797                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6389                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      7384                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      8395                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      8262                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     10480                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      4277                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     3294                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2442                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1850                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1337                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      589                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      613                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1000                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1788                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2652                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3312                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3720                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4067                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4387                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4646                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4886                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5229                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5064                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4400                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4184                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4072                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      128                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      114                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       95                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       77                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       83                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       70                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       66                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       58                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       61                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       54                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       53                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       136638                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      178.677557                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     128.806703                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     198.419690                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          53973     39.50%     39.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        57563     42.13%     81.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        14775     10.81%     92.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1288      0.94%     93.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1420      1.04%     94.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1465      1.07%     95.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1207      0.88%     96.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1190      0.87%     97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3757      2.75%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         136638                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4034                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        68.784581                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       34.732770                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      517.054396                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           4014     99.50%     99.50% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            8      0.20%     99.70% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            5      0.12%     99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-6143            1      0.02%     99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191            3      0.07%     99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::19456-20479            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4034                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4034                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.418691                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.384198                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.147646                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3405     84.41%     84.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  7      0.17%     84.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                450     11.16%     95.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 75      1.86%     97.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 34      0.84%     98.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 21      0.52%     98.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 13      0.32%     99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 12      0.30%     99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  6      0.15%     99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  6      0.15%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  3      0.07%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  2      0.05%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4034                       # Writes before turning the bus around for reads
system.physmem.totQLat                     9487812639                       # Total ticks spent queuing
system.physmem.totMemAccLat               15399143889                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1576355000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       30094.15                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  48844.15                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          49.29                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          10.35                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       49.33                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       10.37                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.47                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.39                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.08                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.56                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.86                       # Average write queue length when enqueuing
system.physmem.readRowHits                     218399                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     26454                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   69.27                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  39.92                       # Row buffer hit rate for writes
system.physmem.avgGap                      1072046.17                       # Average gap between requests
system.physmem.pageHitRate                      64.18                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  517640760                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  282442875                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1231518600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                216464400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            26739576240                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            96784987680                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           160736987250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             286509617805                       # Total energy per rank (pJ)
system.physmem_0.averagePower              699.839198                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   266762765318                       # Time in different power states
system.physmem_0.memoryStateTime::REF     13670540000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    128960598682                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  515168640                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  281094000                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1226955600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                212725440                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            26739576240                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            96280028955                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           161179933500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             286435482375                       # Total energy per rank (pJ)
system.physmem_1.averagePower              699.658112                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   267502793659                       # Time in different power states
system.physmem_1.memoryStateTime::REF     13670540000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    128220707341                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               234006176                       # Number of BP lookups
system.cpu.branchPred.condPredicted         161868409                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          15514584                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            121529948                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               108213709                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             89.042833                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                25036783                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1300149                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  673                       # Number of system calls
system.cpu.numCycles                        818798961                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           84078294                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1200783068                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   234006176                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          133250492                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     718844861                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                31063585                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 2466                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles         3349                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 370656305                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                652882                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          818460793                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.833394                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.163540                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                136795118     16.71%     16.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                223180654     27.27%     43.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 98074923     11.98%     55.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                360410098     44.04%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            818460793                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.285792                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.466518                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                119991092                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             159658898                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 484662986                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              38629701                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               15518116                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             25135087                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 13824                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1248129900                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              39966537                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               15518116                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                176998470                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                78894904                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         210510                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 464956548                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              81882245                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1190637892                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              25457774                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              24955109                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2267146                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               41533192                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1699566                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          1225425199                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5812490436                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1358169789                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          40876588                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                350646969                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               7267                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           7257                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 108140115                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            366205100                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           236096667                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1646330                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5328678                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1168639452                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               12360                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1017122920                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          18523621                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       379926855                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   1032577011                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            206                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     818460793                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.242727                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.084979                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           260810349     31.87%     31.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           227739162     27.83%     59.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           216495712     26.45%     86.14% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            97269955     11.88%     98.03% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            16145606      1.97%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                   9      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       818460793                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                64512117     19.12%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  18144      0.01%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.31% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.31% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead              155573719     46.11%     65.42% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite             116674794     34.58%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             456371749     44.87%     44.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              5195830      0.51%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.06%     45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         2550147      0.25%     46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       11478997      1.13%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            322115143     31.67%     78.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           215585851     21.20%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1017122920                       # Type of FU issued
system.cpu.iq.rate                           1.242213                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   337415663                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.331735                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         3146768879                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1505031237                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    934270592                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads            61877038                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           43565815                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     26152443                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1320728240                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                33810343                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          9960122                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    113964162                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         1106                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        18388                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    107116171                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2065787                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         22375                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               15518116                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                35326355                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 41902                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1168657365                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             366205100                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            236096667                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               6620                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    109                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 45517                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          18388                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       15437362                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3784555                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             19221917                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             974750423                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             303297711                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          42372497                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          5553                       # number of nop insts executed
system.cpu.iew.exec_refs                    497763737                       # number of memory reference insts executed
system.cpu.iew.exec_branches                150613650                       # Number of branches executed
system.cpu.iew.exec_stores                  194466026                       # Number of stores executed
system.cpu.iew.exec_rate                     1.190464                       # Inst execution rate
system.cpu.iew.wb_sent                      963723367                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     960423035                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 536681402                       # num instructions producing a value
system.cpu.iew.wb_consumers                 893284482                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.172966                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.600796                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       357409752                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          15500908                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    767640271                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.027474                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.786859                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    430932808     56.14%     56.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    172476946     22.47%     78.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     73566678      9.58%     88.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     31624021      4.12%     92.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      8540196      1.11%     93.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     14250754      1.86%     95.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      7269409      0.95%     96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      6618976      0.86%     97.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22360483      2.91%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    767640271                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            640654410                       # Number of instructions committed
system.cpu.commit.committedOps              788730069                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      381221434                       # Number of memory references committed
system.cpu.commit.loads                     252240938                       # Number of loads committed
system.cpu.commit.membars                        5740                       # Number of memory barriers committed
system.cpu.commit.branches                  137364859                       # Number of branches committed
system.cpu.commit.fp_insts                   24239771                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 682251399                       # Number of committed integer instructions.
system.cpu.commit.function_calls             19275340                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        385756793     48.91%     48.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         5173441      0.66%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd       637528      0.08%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp      3187668      0.40%     50.05% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt      2550131      0.32%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc     10203074      1.29%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       252240938     31.98%     83.65% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         788730069                       # Class of committed instruction
system.cpu.commit.bw_lim_events              22360483                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1891410858                       # The number of ROB reads
system.cpu.rob.rob_writes                  2343104087                       # The number of ROB writes
system.cpu.timesIdled                          647398                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          338168                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   640649298                       # Number of Instructions Simulated
system.cpu.committedOps                     788724957                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.278077                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.278077                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.782426                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.782426                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                995803851                       # number of integer regfile reads
system.cpu.int_regfile_writes               567906934                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  31889841                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 22959492                       # number of floating regfile writes
system.cpu.cc_regfile_reads                3794434058                       # number of cc regfile reads
system.cpu.cc_regfile_writes                384899317                       # number of cc regfile writes
system.cpu.misc_regfile_reads               715816288                       # number of misc regfile reads
system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2756182                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.932940                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           414226912                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2756694                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            150.262202                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         257775000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.932940                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999869                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          222                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         839344268                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        839344268                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    286295518                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       286295518                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    127916671                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      127916671                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         3177                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          3177                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     414212189                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        414212189                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    414215366                       # number of overall hits
system.cpu.dcache.overall_hits::total       414215366                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      3031489                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       3031489                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1034806                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1034806                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          647                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          647                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4066295                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4066295                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4066942                       # number of overall misses
system.cpu.dcache.overall_misses::total       4066942                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  35316006617                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  35316006617                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10004118304                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10004118304                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       202750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       202750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  45320124921                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  45320124921                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  45320124921                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  45320124921                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    289327007                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    289327007                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         3824                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         3824                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    418278484                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    418278484                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    418282308                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    418282308                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010478                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.010478                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008025                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.008025                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169195                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.169195                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009722                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009722                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009723                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009723                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11649.722832                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11649.722832                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9667.626883                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  9667.626883                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67583.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67583.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11145.311622                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 11145.311622                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11143.538541                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 11143.538541                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       349732                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets            5194                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    67.333847                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       735277                       # number of writebacks
system.cpu.dcache.writebacks::total            735277                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       996280                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       996280                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       313945                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       313945                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1310225                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1310225                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1310225                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1310225                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035209                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      2035209                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720861                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       720861                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          641                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          641                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2756070                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2756070                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2756711                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2756711                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23121613833                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  23121613833                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5599042571                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5599042571                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5366500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5366500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28720656404                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  28720656404                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28726022904                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  28726022904                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005590                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005590                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.167626                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.167626                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006591                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006591                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11360.805614                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11360.805614                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  7767.159787                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  7767.159787                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8372.074883                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8372.074883                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10420.873346                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10420.873346                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10420.396953                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10420.396953                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           5169874                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.641329                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           365482216                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           5170384                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             70.687635                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle         247770250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.641329                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997346                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997346                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          328                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         746482947                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        746482947                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    365482251                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       365482251                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     365482251                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        365482251                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    365482251                       # number of overall hits
system.cpu.icache.overall_hits::total       365482251                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      5174022                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       5174022                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      5174022                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        5174022                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      5174022                       # number of overall misses
system.cpu.icache.overall_misses::total       5174022                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  41654200685                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  41654200685                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  41654200685                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  41654200685                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  41654200685                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  41654200685                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    370656273                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    370656273                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    370656273                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    370656273                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    370656273                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    370656273                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013959                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.013959                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.013959                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.013959                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.013959                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.013959                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8050.642360                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  8050.642360                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  8050.642360                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  8050.642360                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  8050.642360                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  8050.642360                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        76485                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          100                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              3140                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    24.358280                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets           20                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3620                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3620                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3620                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3620                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3620                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3620                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5170402                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      5170402                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      5170402                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      5170402                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      5170402                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      5170402                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  36439121179                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  36439121179                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  36439121179                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  36439121179                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  36439121179                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  36439121179                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013949                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013949                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013949                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.013949                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013949                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.013949                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7047.637917                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7047.637917                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7047.637917                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  7047.637917                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7047.637917                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  7047.637917                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued      1347058                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      1355234                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         7153                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage      4790478                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           299258                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16361.552831                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            7824313                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           315622                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            24.790138                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      13409363000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   738.976811                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   129.067019                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8785.583028                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6707.925973                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.045104                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007878                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.536229                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.409419                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.998630                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022         6482                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         9882                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2          155                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1470                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4840                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          226                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2079                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7315                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.395630                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.603149                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        139634451                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       139634451                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst      5166743                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1926167                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        7092910                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       735277                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       735277                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       718012                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       718012                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst      5166743                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2644179                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7810922                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      5166743                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2644179                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7810922                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         3643                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       109683                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       113326                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data           16                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           16                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2832                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2832                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3643                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       112515                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        116158                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3643                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       112515                       # number of overall misses
system.cpu.l2cache.overall_misses::total       116158                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    270029959                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   8565404562                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   8835434521                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    207607487                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    207607487                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    270029959                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   8773012049                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   9043042008                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    270029959                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   8773012049                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   9043042008                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst      5170386                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      2035850                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7206236                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       735277                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       735277                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       720844                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       720844                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      5170386                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2756694                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      7927080                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      5170386                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2756694                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      7927080                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.000705                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.053876                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.015726                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.941176                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.941176                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003929                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.003929                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.000705                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.040815                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.014653                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.000705                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.040815                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.014653                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74122.964315                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.362189                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77964.761140                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73307.728460                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73307.728460                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74122.964315                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77971.933067                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 77851.219959                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74122.964315                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77971.933067                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 77851.219959                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66326                       # number of writebacks
system.cpu.l2cache.writebacks::total            66326                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           15                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data         1303                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total         1318                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1445                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         1445                       # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         2748                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         2763                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           15                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         2748                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         2763                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3628                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       108380                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       112008                       # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202241                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       202241                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1387                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1387                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3628                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       109767                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       113395                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3628                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       109767                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202241                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       315636                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    238098541                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   7611970750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7850069291                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  17087057356                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  17087057356                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       219516                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       219516                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    114561754                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    114561754                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    238098541                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7726532504                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   7964631045                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    238098541                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7726532504                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  17087057356                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  25051688401                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.000702                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.053236                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.015543                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.941176                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.941176                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001924                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001924                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000702                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039818                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.014305                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000702                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039818                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.039817                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65628.043275                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70234.090699                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70084.898320                       # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84488.592105                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13719.750000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13719.750000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82596.794521                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82596.794521                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65628.043275                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70390.304044                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.938578                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65628.043275                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70390.304044                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79368.919898                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq        7206252                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       7206251                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       735277                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       248818                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       720844                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       720844                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     10340787                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6248699                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          16589486                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330904640                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223486144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          554390784                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      248834                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      8911208                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.027922                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.164749                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            8662390     97.21%     97.21% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4             248818      2.79%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        8911208                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     5066472000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    7756152507                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    4138701196                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.membus.trans_dist::ReadReq              314173                       # Transaction distribution
system.membus.trans_dist::ReadResp             314173                       # Transaction distribution
system.membus.trans_dist::Writeback             66326                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1387                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1387                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       697478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 697478                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24440704                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                24440704                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            381902                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  381902    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              381902                       # Request fanout histogram
system.membus.reqLayer0.occupancy           746879857                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1648874306                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)

---------- End Simulation Statistics   ----------