path: root/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.410968                       # Number of seconds simulated
sim_ticks                                410968419000                       # Number of ticks simulated
final_tick                               410968419000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  85599                       # Simulator instruction rate (inst/s)
host_op_rate                                   105384                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               54910730                       # Simulator tick rate (ticks/s)
host_mem_usage                                 322152                       # Number of bytes of host memory used
host_seconds                                  7484.30                       # Real time elapsed on the host
sim_insts                                   640649299                       # Number of instructions simulated
sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            226432                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7007424                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher     12927040                       # Number of bytes read from this memory
system.physmem.bytes_read::total             20160896                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       226432                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          226432                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4244672                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4244672                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               3538                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             109491                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher       201985                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                315014                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66323                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66323                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               550972                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             17051004                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher     31455069                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                49057044                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          550972                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             550972                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          10328463                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               10328463                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          10328463                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              550972                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            17051004                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher     31455069                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               59385507                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        315014                       # Number of read requests accepted
system.physmem.writeReqs                        66323                       # Number of write requests accepted
system.physmem.readBursts                      315014                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66323                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 20141440                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     19456                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4238400                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  20160896                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4244672                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      304                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                      67                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs             16                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               19880                       # Per bank write bursts
system.physmem.perBankRdBursts::1               19436                       # Per bank write bursts
system.physmem.perBankRdBursts::2               19769                       # Per bank write bursts
system.physmem.perBankRdBursts::3               19866                       # Per bank write bursts
system.physmem.perBankRdBursts::4               19687                       # Per bank write bursts
system.physmem.perBankRdBursts::5               20154                       # Per bank write bursts
system.physmem.perBankRdBursts::6               19548                       # Per bank write bursts
system.physmem.perBankRdBursts::7               19410                       # Per bank write bursts
system.physmem.perBankRdBursts::8               19409                       # Per bank write bursts
system.physmem.perBankRdBursts::9               19464                       # Per bank write bursts
system.physmem.perBankRdBursts::10              19401                       # Per bank write bursts
system.physmem.perBankRdBursts::11              19757                       # Per bank write bursts
system.physmem.perBankRdBursts::12              19512                       # Per bank write bursts
system.physmem.perBankRdBursts::13              19953                       # Per bank write bursts
system.physmem.perBankRdBursts::14              19499                       # Per bank write bursts
system.physmem.perBankRdBursts::15              19965                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4261                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4104                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4143                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4151                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4243                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4228                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4095                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4094                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4153                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    410968364500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  315014                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66323                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    121710                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    120019                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     14305                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      6741                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6431                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      7602                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      8833                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      9380                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      8107                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      3875                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     2934                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     2149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1601                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1023                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      599                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     1802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     2657                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3315                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3782                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4123                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4657                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5078                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5221                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5014                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4948                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4245                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4091                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4048                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      119                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      110                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      102                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       84                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       79                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       88                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       90                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       81                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       74                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       68                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       65                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       76                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       59                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       56                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       51                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                       48                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       136515                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      178.576479                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     128.708862                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     198.239774                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          54117     39.64%     39.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        57190     41.89%     81.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        14847     10.88%     92.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1353      0.99%     93.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1460      1.07%     94.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1428      1.05%     95.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1211      0.89%     96.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1099      0.81%     97.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         3810      2.79%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         136515                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4034                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        69.350768                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       34.698276                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      557.584511                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           4013     99.48%     99.48% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            9      0.22%     99.70% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            4      0.10%     99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119            3      0.07%     99.88% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191            1      0.02%     99.90% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::11264-12287            2      0.05%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-15359            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4034                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4034                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.416708                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.380496                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.197000                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3413     84.61%     84.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 10      0.25%     84.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                440     10.91%     95.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                 77      1.91%     97.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 36      0.89%     98.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 18      0.45%     99.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 14      0.35%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 10      0.25%     99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  4      0.10%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  2      0.05%     99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  3      0.07%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  4      0.10%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  1      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4034                       # Writes before turning the bus around for reads
system.physmem.totQLat                     8815753021                       # Total ticks spent queuing
system.physmem.totMemAccLat               14716565521                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1573550000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       28012.31                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  46762.31                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          49.01                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                          10.31                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       49.06                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                       10.33                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.46                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.08                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.55                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.40                       # Average write queue length when enqueuing
system.physmem.readRowHits                     218109                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     26303                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   69.30                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  39.70                       # Row buffer hit rate for writes
system.physmem.avgGap                      1077703.88                       # Average gap between requests
system.physmem.pageHitRate                      64.16                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  518041440                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  282661500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1230403200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                216432000                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            26842305360                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            96374724480                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           162040566750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             287505134730                       # Total energy per rank (pJ)
system.physmem_0.averagePower              699.583184                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   268934392735                       # Time in different power states
system.physmem_0.memoryStateTime::REF     13723060000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    128308892015                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  513943920                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  280425750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1224030600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                212706000                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            26842305360                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            96023770920                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           162348426750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             287445609300                       # Total energy per rank (pJ)
system.physmem_1.averagePower              699.438325                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   269449023468                       # Time in different power states
system.physmem_1.memoryStateTime::REF     13723060000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    127794271282                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               234596987                       # Number of BP lookups
system.cpu.branchPred.condPredicted         161823961                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          15514568                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            122849584                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               109536151                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             89.162818                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                25674290                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            1300140                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  673                       # Number of system calls
system.cpu.numCycles                        821936839                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           85359069                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     1200718249                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   234596987                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          135210441                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     720713354                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                31063509                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 2336                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles         3414                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 371348285                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                652804                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          821609958                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.824964                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.165392                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                139667844     17.00%     17.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                223418217     27.19%     44.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 99581089     12.12%     56.31% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                358942808     43.69%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            821609958                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.285420                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.460840                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                121271680                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             161528221                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 484660379                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              38631604                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles               15518074                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             25181978                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 13827                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1248136929                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              39965779                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles               15518074                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                178276857                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                80769172                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         209944                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 464321622                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              82514289                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1190649625                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              25545503                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents              24955076                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                2266892                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents               41524383                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                1701930                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands          1225389846                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            5812446196                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1358179405                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          40876479                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                350611616                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts               7266                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts           7257                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 108773290                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            366116518                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           236097454                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1660812                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          5332652                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1168559259                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               12361                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1017121345                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          18467813                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       379846662                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   1032147150                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            207                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     821609958                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.237961                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.084868                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           263952395     32.13%     32.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           227112360     27.64%     59.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           217754382     26.50%     86.27% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            96663071     11.77%     98.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4            16127742      1.96%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                   8      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       821609958                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                63877670     18.90%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  18143      0.01%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.90% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.09% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.09% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead              157438093     46.58%     65.67% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite             116037067     34.33%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             456371832     44.87%     44.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              5195828      0.51%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.06%     45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         2550148      0.25%     46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       11478997      1.13%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.14% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            322111232     31.67%     78.80% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           215588105     21.20%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1017121345                       # Type of FU issued
system.cpu.iq.rate                           1.237469                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   338007862                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.332318                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         3150451328                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1504870795                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    934275536                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads            61876995                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           43565857                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     26152450                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1321318894                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                33810313                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          9960669                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    113875580                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         1094                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        18373                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    107116958                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2065804                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         20149                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles               15518074                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                35327155                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 46316                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1168577176                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             366116518                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            236097454                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts               6621                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                    106                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 49932                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          18373                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       15437332                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3784565                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             19221897                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             974752675                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             303297711                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          42368670                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          5556                       # number of nop insts executed
system.cpu.iew.exec_refs                    497765117                       # number of memory reference insts executed
system.cpu.iew.exec_branches                150613949                       # Number of branches executed
system.cpu.iew.exec_stores                  194467406                       # Number of stores executed
system.cpu.iew.exec_rate                     1.185922                       # Inst execution rate
system.cpu.iew.wb_sent                      963726327                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     960427986                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 536047777                       # num instructions producing a value
system.cpu.iew.wb_consumers                 893284950                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.168494                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.600086                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       357420302                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          15500888                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    770788105                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.023277                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.776928                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    432159906     56.07%     56.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    174391468     22.63%     78.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     72936790      9.46%     88.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     32897876      4.27%     92.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      8538896      1.11%     93.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     14258442      1.85%     95.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      7269703      0.94%     96.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      5974810      0.78%     97.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     22360214      2.90%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    770788105                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      381221434                       # Number of memory references committed
system.cpu.commit.loads                     252240938                       # Number of loads committed
system.cpu.commit.membars                        5740                       # Number of memory barriers committed
system.cpu.commit.branches                  137364860                       # Number of branches committed
system.cpu.commit.fp_insts                   24239771                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 682251399                       # Number of committed integer instructions.
system.cpu.commit.function_calls             19275340                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        385756794     48.91%     48.91% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         5173441      0.66%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     49.56% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd       637528      0.08%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     49.65% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp      3187668      0.40%     50.05% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt      2550131      0.32%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     50.37% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc     10203074      1.29%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     51.67% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       252240938     31.98%     83.65% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
system.cpu.commit.bw_lim_events              22360214                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   1894569512                       # The number of ROB reads
system.cpu.rob.rob_writes                  2343126520                       # The number of ROB writes
system.cpu.timesIdled                          647387                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          326881                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.282975                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.282975                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.779439                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.779439                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                995803218                       # number of integer regfile reads
system.cpu.int_regfile_writes               567908989                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  31889842                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 22959495                       # number of floating regfile writes
system.cpu.cc_regfile_reads                3794442903                       # number of cc regfile reads
system.cpu.cc_regfile_writes                384898512                       # number of cc regfile writes
system.cpu.misc_regfile_reads               715818410                       # number of misc regfile reads
system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           2756184                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.933181                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           414216914                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           2756696                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            150.258467                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         257783000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.933181                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999869                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999869                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          223                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          192                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         839346712                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        839346712                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    286294274                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       286294274                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    127907939                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      127907939                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         3157                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          3157                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     414202213                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        414202213                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    414205370                       # number of overall hits
system.cpu.dcache.overall_hits::total       414205370                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      3033975                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       3033975                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1043538                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1043538                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          646                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          646                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      4077513                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        4077513                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      4078159                       # number of overall misses
system.cpu.dcache.overall_misses::total       4078159                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  35335718000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  35335718000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10020788350                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10020788350                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       187500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       187500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  45356506350                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  45356506350                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  45356506350                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  45356506350                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    289328249                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    289328249                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         3803                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         3803                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    418279726                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    418279726                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    418283529                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    418283529                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010486                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.010486                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008092                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.008092                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169866                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.169866                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.009748                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.009748                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.009750                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.009750                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11646.674083                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11646.674083                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9602.705747                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total  9602.705747                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        62500                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        62500                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11123.571243                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 11123.571243                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11121.809216                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 11121.809216                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets       355417                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets            4792                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    74.168823                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       735485                       # number of writebacks
system.cpu.dcache.writebacks::total            735485                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       998769                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       998769                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       322672                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       322672                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1321441                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1321441                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1321441                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1321441                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035206                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      2035206                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       720866                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       720866                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          641                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          641                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2756072                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2756072                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2756713                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2756713                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24128110500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  24128110500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5958496350                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5958496350                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5922000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5922000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  30086606850                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  30086606850                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  30092528850                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  30092528850                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005590                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005590                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168551                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168551                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006591                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.006591                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11855.365255                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11855.365255                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8265.747518                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8265.747518                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  9238.689548                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  9238.689548                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10916.480720                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10916.480720                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10916.090594                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10916.090594                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements           5169351                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.555311                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           366173734                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs           5169861                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             70.828545                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle         247765500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.555311                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997178                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997178                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          119                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          327                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         747866384                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        747866384                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    366173762                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       366173762                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     366173762                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        366173762                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    366173762                       # number of overall hits
system.cpu.icache.overall_hits::total       366173762                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst      5174491                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total       5174491                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst      5174491                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total        5174491                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst      5174491                       # number of overall misses
system.cpu.icache.overall_misses::total       5174491                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst  41645043922                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total  41645043922                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst  41645043922                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total  41645043922                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst  41645043922                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total  41645043922                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    371348253                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    371348253                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    371348253                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    371348253                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    371348253                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    371348253                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013934                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.013934                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.013934                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.013934                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.013934                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.013934                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8048.143078                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total  8048.143078                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst  8048.143078                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total  8048.143078                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst  8048.143078                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total  8048.143078                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        82369                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          103                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              3794                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    21.710332                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    20.600000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4612                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         4612                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         4612                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         4612                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         4612                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         4612                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5169879                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total      5169879                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst      5169879                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total      5169879                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst      5169879                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total      5169879                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  39015177435                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total  39015177435                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst  39015177435                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total  39015177435                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst  39015177435                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total  39015177435                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013922                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013922                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013922                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.013922                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013922                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.013922                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7546.632607                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7546.632607                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7546.632607                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  7546.632607                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7546.632607                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  7546.632607                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued      1349974                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified      1355118                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         4500                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage      4790050                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           298717                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16361.529179                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           14361886                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           315081                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            45.581568                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      18036523000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks   748.333626                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst   127.076161                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  8786.065763                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6700.053629                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.045675                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007756                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.536259                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.408939                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.998628                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022         6481                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         9883                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           14                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2          157                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1434                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4876                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          165                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          227                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2102                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7295                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.395569                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.603210                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        244360860                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       244360860                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks       735485                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       735485                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       718367                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       718367                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      5166316                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total      5166316                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1926758                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      1926758                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst      5166316                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      2645125                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         7811441                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst      5166316                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      2645125                       # number of overall hits
system.cpu.l2cache.overall_hits::total        7811441                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data           16                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total           16                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data         2482                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total         2482                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3547                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         3547                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       109089                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       109089                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         3547                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       111571                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        115118                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         3547                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       111571                       # number of overall misses
system.cpu.l2cache.overall_misses::total       115118                       # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        23000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    204363000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total    204363000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    262565000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    262565000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   8229036500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   8229036500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    262565000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   8433399500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   8695964500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    262565000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   8433399500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   8695964500                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks       735485                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       735485                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           17                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       720849                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       720849                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      5169863                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total      5169863                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2035847                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      2035847                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst      5169863                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2756696                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      7926559                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst      5169863                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2756696                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      7926559                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.941176                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.941176                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003443                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.003443                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.000686                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.000686                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.053584                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.053584                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.000686                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.040473                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.014523                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.000686                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.040473                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.014523                       # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1437.500000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1437.500000                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82338.033844                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82338.033844                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74024.527770                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74024.527770                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75434.154681                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75434.154681                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74024.527770                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75587.737853                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75539.572439                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74024.527770                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75587.737853                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75539.572439                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66323                       # number of writebacks
system.cpu.l2cache.writebacks::total            66323                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1105                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         1105                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            9                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          975                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          975                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            9                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         2080                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         2089                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            9                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         2080                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         2089                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         8868                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         8868                       # number of CleanEvict MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       202062                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       202062                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1377                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         1377                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3538                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3538                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       108114                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       108114                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         3538                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       109491                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       113029                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         3538                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       109491                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       202062                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       315091                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  17000279164                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  17000279164                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       275000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       275000                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    139099000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    139099000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    240756500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    240756500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   7531984000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   7531984000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    240756500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7671083000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   7911839500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    240756500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7671083000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  17000279164                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  24912118664                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.941176                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.941176                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001910                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001910                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.000684                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.053105                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.053105                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.039718                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.014260                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000684                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.039718                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.039751                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84133.974542                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17187.500000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17187.500000                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 101015.976761                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 101015.976761                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68048.756360                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68048.756360                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69667.055145                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69667.055145                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68048.756360                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70061.310975                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69998.314592                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68048.756360                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70061.310975                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79063.250502                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests     15852127                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests      7925581                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests       644320                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         9549                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         9495                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           54                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp       7205725                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       801808                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      6778141                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       245737                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           17                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       720849                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       720849                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq      5169879                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      2035847                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     15508216                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7626183                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          23134399                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    330871168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    223499584                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          554370752                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      544470                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     16396581                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.079179                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.270031                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           15098363     92.08%     92.08% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            1298164      7.92%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                 54      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       16396581                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     8661548500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy    7754847439                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.9                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    4135063977                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             313637                       # Transaction distribution
system.membus.trans_dist::Writeback             66323                       # Transaction distribution
system.membus.trans_dist::CleanEvict           231789                       # Transaction distribution
system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              16                       # Transaction distribution
system.membus.trans_dist::ReadExReq              1377                       # Transaction distribution
system.membus.trans_dist::ReadExResp             1377                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        313637                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       928172                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 928172                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     24405568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                24405568                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            613142                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  613142    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              613142                       # Request fanout histogram
system.membus.reqLayer0.occupancy           975944720                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1649749525                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)

---------- End Simulation Statistics   ----------